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Searched refs:pin (Results 1 – 18 of 18) sorted by relevance

/hal_nxp-2.7.6/imx/drivers/
Dgpio_imx.c49 uint32_t pin; in GPIO_Init() local
57 pin = initConfig->pin; in GPIO_Init()
61 GPIO_GDIR_REG(base) |= (1U << pin); in GPIO_Init()
63 GPIO_GDIR_REG(base) &= ~(1U << pin); in GPIO_Init()
66 if(pin < 16) in GPIO_Init()
71 pin -= 16; in GPIO_Init()
77 *icr &= ~(0x3<<(2*pin)); in GPIO_Init()
82 *icr = (*icr & (~(0x3<<(2*pin)))) | (0x1<<(2*pin)); in GPIO_Init()
87 *icr = (*icr & (~(0x3<<(2*pin)))) | (0x2<<(2*pin)); in GPIO_Init()
92 *icr |= (0x3<<(2*pin)); in GPIO_Init()
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Dgpio_imx.h75 uint32_t pin; /*!< Specifies the pin number. */ member
117 static inline uint8_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) in GPIO_ReadPinInput() argument
119 assert(pin < 32); in GPIO_ReadPinInput()
121 return (uint8_t)((GPIO_DR_REG(base) >> pin) & 1U); in GPIO_ReadPinInput()
143 static inline uint8_t GPIO_ReadPinOutput(GPIO_Type* base, uint32_t pin) in GPIO_ReadPinOutput() argument
145 assert(pin < 32); in GPIO_ReadPinOutput()
147 return (uint8_t)((GPIO_DR_REG(base) >> pin) & 0x1U); in GPIO_ReadPinOutput()
169 void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal);
197 static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) in GPIO_ReadPadStatus() argument
199 assert(pin < 32); in GPIO_ReadPadStatus()
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/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_gpio.c97 void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) in GPIO_PinInit() argument
104 base->DIRCLR[port] = 1UL << pin; in GPIO_PinInit()
106 base->DIR[port] &= ~(1UL << pin); in GPIO_PinInit()
114 base->CLR[port] = (1UL << pin); in GPIO_PinInit()
118 base->SET[port] = (1UL << pin); in GPIO_PinInit()
122 base->DIRSET[port] = 1UL << pin; in GPIO_PinInit()
124 base->DIR[port] |= 1UL << pin; in GPIO_PinInit()
138 void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config… in GPIO_SetPinInterruptConfig() argument
140 base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); in GPIO_SetPinInterruptConfig()
142 base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); in GPIO_SetPinInterruptConfig()
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Dfsl_gpio.h136 void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
153 static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) in GPIO_PinWrite() argument
155 base->B[port][pin] = output; in GPIO_PinWrite()
172 static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) in GPIO_PinRead() argument
174 return (uint32_t)base->B[port][pin]; in GPIO_PinRead()
278 void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config…
329 void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
339 void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
350 void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
Dfsl_iopctl.h42 uint32_t pin : 32; /* Pin number */ member
88 __STATIC_INLINE void IOPCTL_PinMuxSet(IOPCTL_Type *base, uint8_t port, uint8_t pin, uint32_t modefu… in IOPCTL_PinMuxSet() argument
90 base->PIO[port][pin] = modefunc; in IOPCTL_PinMuxSet()
106 IOPCTL_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); in IOPCTL_SetPinMuxing()
/hal_nxp-2.7.6/mcux/drivers/lpc/
Dfsl_gpio.c97 void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) in GPIO_PinInit() argument
104 base->DIRCLR[port] = 1UL << pin; in GPIO_PinInit()
106 base->DIR[port] &= ~(1UL << pin); in GPIO_PinInit()
114 base->CLR[port] = (1UL << pin); in GPIO_PinInit()
118 base->SET[port] = (1UL << pin); in GPIO_PinInit()
122 base->DIRSET[port] = 1UL << pin; in GPIO_PinInit()
124 base->DIR[port] |= 1UL << pin; in GPIO_PinInit()
138 void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config… in GPIO_SetPinInterruptConfig() argument
140 base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); in GPIO_SetPinInterruptConfig()
142 base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); in GPIO_SetPinInterruptConfig()
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Dfsl_gpio.h136 void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
153 static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output) in GPIO_PinWrite() argument
155 base->B[port][pin] = output; in GPIO_PinWrite()
172 static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin) in GPIO_PinRead() argument
174 return (uint32_t)base->B[port][pin]; in GPIO_PinRead()
278 void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config…
329 void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
339 void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
350 void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
Dfsl_iocon.h42 uint8_t pin; /* Pin number */ member
182 __STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
184 base->PIO[port][pin] = modefunc;
204 IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc); in IOCON_SetPinMuxing()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_gpio.c71 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) in GPIO_PinInit() argument
85 base->IMR &= ~(1UL << pin); in GPIO_PinInit()
90 base->GDIR &= ~(1UL << pin); in GPIO_PinInit()
94 GPIO_PinWrite(base, pin, Config->outputLogic); in GPIO_PinInit()
95 base->GDIR |= (1UL << pin); in GPIO_PinInit()
99 GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); in GPIO_PinInit()
111 void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_PinWrite() argument
113 assert(pin < 32U); in GPIO_PinWrite()
117 base->DR_CLEAR = (1UL << pin); in GPIO_PinWrite()
119 base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ in GPIO_PinWrite()
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Dfsl_gpio.h78 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config);
95 void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
101 static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_WritePinOutput() argument
103 GPIO_PinWrite(base, pin, output); in GPIO_WritePinOutput()
176 static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) in GPIO_PinRead() argument
178 assert(pin < 32U); in GPIO_PinRead()
180 return (((base->DR) >> pin) & 0x1U); in GPIO_PinRead()
187 static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) in GPIO_ReadPinInput() argument
189 return GPIO_PinRead(base, pin); in GPIO_ReadPinInput()
205 static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) in GPIO_PinReadPadStatus() argument
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Dfsl_snvs_lp.c294 int pin; in SNVS_LP_SRTC_Init() local
302 for (pin = (int32_t)kSNVS_ExternalTamper1; pin <= (int32_t)SNVS_LP_MAX_TAMPER; pin++) in SNVS_LP_SRTC_Init()
304 SNVS_LP_DisableExternalTamper(SNVS, (snvs_lp_external_tamper_t)pin); in SNVS_LP_SRTC_Init()
305 SNVS_LP_ClearExternalTamperStatus(SNVS, (snvs_lp_external_tamper_t)pin); in SNVS_LP_SRTC_Init()
609 void SNVS_LP_EnablePassiveTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin, snvs_lp_passive_ta… in SNVS_LP_EnablePassiveTamper() argument
611 switch (pin) in SNVS_LP_EnablePassiveTamper()
791 void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin) in SNVS_LP_DisableExternalTamper() argument
793 switch (pin) in SNVS_LP_DisableExternalTamper()
840 for (int pin = (int8_t)kSNVS_ExternalTamper1; pin <= (int8_t)SNVS_LP_MAX_TAMPER; pin++) in SNVS_LP_DisableAllExternalTamper() local
842 SNVS_LP_DisableExternalTamper(SNVS, (snvs_lp_external_tamper_t)pin); in SNVS_LP_DisableAllExternalTamper()
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Dfsl_snvs_lp.h406 void SNVS_LP_EnablePassiveTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin, snvs_lp_passive_ta…
417 snvs_lp_active_tx_tamper_t pin,
520 void SNVS_LP_DisableExternalTamper(SNVS_Type *base, snvs_lp_external_tamper_t pin);
537 …al_tamper_status_t SNVS_LP_GetExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin);
545 void SNVS_LP_ClearExternalTamperStatus(SNVS_Type *base, snvs_lp_external_tamper_t pin);
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_gpio.h146 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
162 static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_PinWrite() argument
167 base->PCOR = GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
171 base->PSOR = GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
176 base->PDOR |= GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
180 base->PDOR &= ~GPIO_FIT_REG(1UL << pin); in GPIO_PinWrite()
244 static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) in GPIO_PinRead() argument
246 return (((uint32_t)(base->PDIR) >> pin) & 0x01UL); in GPIO_PinRead()
298 static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_… in GPIO_SetPinInterruptConfig() argument
302 base->ICR[pin] = GPIO_FIT_REG((base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | GPIO_ICR_IRQC(config)); in GPIO_SetPinInterruptConfig()
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Dfsl_port.h271 static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config) in PORT_SetPinConfig() argument
274 uint32_t addr = (uint32_t)&base->PCR[pin]; in PORT_SetPinConfig()
374 static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux) in PORT_SetPinMux() argument
376 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux); in PORT_SetPinMux()
443 static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t confi… in PORT_SetPinInterruptConfig() argument
445 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config); in PORT_SetPinInterruptConfig()
459 static inline void PORT_SetPinDriveStrength(PORT_Type *base, uint32_t pin, uint8_t strength) in PORT_SetPinDriveStrength() argument
461 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE_MASK) | PORT_PCR_DSE(strength); in PORT_SetPinDriveStrength()
473 static inline void PORT_EnablePinDoubleDriveStrength(PORT_Type *base, uint32_t pin, bool enable) in PORT_EnablePinDoubleDriveStrength() argument
475 base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_DSE1_MASK) | PORT_PCR_DSE1(enable); in PORT_EnablePinDoubleDriveStrength()
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Dfsl_gpio.c98 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) in GPIO_PinInit() argument
104 base->PDDR &= GPIO_FIT_REG(~(1UL << pin)); in GPIO_PinInit()
108 GPIO_PinWrite(base, pin, config->outputLogic); in GPIO_PinInit()
109 base->PDDR |= GPIO_FIT_REG((1UL << pin)); in GPIO_PinInit()
156 uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin) in GPIO_PinGetInterruptFlag() argument
158 return (uint8_t)((base->ICR[pin] & GPIO_ICR_ISF_MASK) >> GPIO_ICR_ISF_SHIFT); in GPIO_PinGetInterruptFlag()
195 void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t pin) in GPIO_PinClearInterruptFlag() argument
197 base->ICR[pin] |= GPIO_FIT_REG(GPIO_ICR_ISF(1U)); in GPIO_PinClearInterruptFlag()
308 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config) in FGPIO_PinInit() argument
314 base->PDDR &= ~(1UL << pin); in FGPIO_PinInit()
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/hal_nxp-2.7.6/mcux/drivers/imx8/
Dfsl_gpio.h78 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config);
95 void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
101 static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_WritePinOutput() argument
103 GPIO_PinWrite(base, pin, output); in GPIO_WritePinOutput()
174 static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin) in GPIO_PinRead() argument
176 assert(pin < 32U); in GPIO_PinRead()
178 return (((base->DR) >> pin) & 0x1U); in GPIO_PinRead()
185 static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin) in GPIO_ReadPinInput() argument
187 return GPIO_PinRead(base, pin); in GPIO_ReadPinInput()
203 static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin) in GPIO_PinReadPadStatus() argument
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Dfsl_gpio.c71 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config) in GPIO_PinInit() argument
85 base->IMR &= ~(1UL << pin); in GPIO_PinInit()
90 base->GDIR &= ~(1UL << pin); in GPIO_PinInit()
94 GPIO_PinWrite(base, pin, Config->outputLogic); in GPIO_PinInit()
95 base->GDIR |= (1UL << pin); in GPIO_PinInit()
99 GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode); in GPIO_PinInit()
111 void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) in GPIO_PinWrite() argument
113 assert(pin < 32U); in GPIO_PinWrite()
116 base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ in GPIO_PinWrite()
120 base->DR |= (1UL << pin); /* Set pin output to high level.*/ in GPIO_PinWrite()
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/hal_nxp-2.7.6/dts/nxp/kinetis/
DMKW40Z160VHT4-pinctrl.dtsi7 /* This file is handcoded based on what pin configurations are actually