1 /*
2 * Copyright 2017-2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_PXP_H_
10 #define _FSL_PXP_H_
11
12 #include "fsl_common.h"
13
14 /* Compatibility macro map. */
15 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK))
16 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
17 #endif
18
19 #if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK))
20 #define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
21 #endif
22
23 #if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK))
24 #define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK
25 #endif
26
27 #if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK))
28 #define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK
29 #endif
30
31 #if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK))
32 #define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK
33 #endif
34
35 /*!
36 * @addtogroup pxp_driver
37 * @{
38 */
39
40 /*******************************************************************************
41 * Definitions
42 ******************************************************************************/
43
44 /* PXP global LUT table is 16K. */
45 #define PXP_LUT_TABLE_BYTE (16 * 1024)
46 /* Intenral memory for LUT, the size is 256 bytes. */
47 #define PXP_INTERNAL_RAM_LUT_BYTE (256)
48
49 /*! @name Driver version */
50 /*@{*/
51 #define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
52 /*@}*/
53
54 /* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */
55 #if defined(PXP_CTRL_ROT_POS_MASK)
56 #define PXP_SHARE_ROTATE 1
57 #else
58 #define PXP_SHARE_ROTATE 0
59 #endif
60
61 /*! @brief PXP interrupts to enable. */
62 enum _pxp_interrupt_enable
63 {
64 kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, /*!< Interrupt to show that the command set
65 by @ref PXP_SetNextCommand has been loaded. */
66 kPXP_CompleteInterruptEnable = PXP_CTRL_IRQ_ENABLE_MASK, /*!< PXP process completed. */
67 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
68 kPXP_LutDmaLoadInterruptEnable = PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, /*!< The LUT table has been loaded by DMA. */
69 #endif
70 };
71
72 /*!
73 * @brief PXP status flags.
74 *
75 * @note These enumerations are meant to be OR'd together to form a bit mask.
76 */
77 enum _pxp_flags
78 {
79 kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, /*!< The command set by @ref PXP_SetNextCommand
80 has been loaded, could set new command. */
81 kPXP_CompleteFlag = PXP_STAT_IRQ0_MASK, /*!< PXP process completed. */
82 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
83 kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, /*!< The LUT table has been loaded by DMA. */
84 #endif
85 kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK, /*!< PXP encountered an AXI read error
86 and processing has been terminated. */
87 kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, /*!< PXP encountered an AXI write error
88 and processing has been terminated. */
89 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
90 kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK, /*!< PXP encountered an AXI read error
91 and processing has been terminated. */
92 kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, /*!< PXP encountered an AXI write error
93 and processing has been terminated. */
94 #endif
95 };
96
97 /*! @brief PXP output flip mode. */
98 typedef enum _pxp_flip_mode
99 {
100 kPXP_FlipDisable = 0U, /*!< Flip disable. */
101 kPXP_FlipHorizontal = 0x01U, /*!< Horizontal flip. */
102 kPXP_FlipVertical = 0x02U, /*!< Vertical flip. */
103 kPXP_FlipBoth = 0x03U, /*!< Flip both directions. */
104 } pxp_flip_mode_t;
105
106 /*! @brief PXP rotate mode. */
107 typedef enum _pxp_rotate_position
108 {
109 kPXP_RotateOutputBuffer = 0U, /*!< Rotate the output buffer. */
110 kPXP_RotateProcessSurface, /*!< Rotate the process surface. */
111 } pxp_rotate_position_t;
112
113 /*! @brief PXP rotate degree. */
114 typedef enum _pxp_rotate_degree
115 {
116 kPXP_Rotate0 = 0U, /*!< Clock wise rotate 0 deg. */
117 kPXP_Rotate90, /*!< Clock wise rotate 90 deg. */
118 kPXP_Rotate180, /*!< Clock wise rotate 180 deg. */
119 kPXP_Rotate270, /*!< Clock wise rotate 270 deg. */
120 } pxp_rotate_degree_t;
121
122 /*! @brief PXP interlaced output mode. */
123 typedef enum _pxp_interlaced_output_mode
124 {
125 kPXP_OutputProgressive = 0U, /*!< All data written in progressive format to output buffer 0. */
126 kPXP_OutputField0, /*!< Only write field 0 data to output buffer 0. */
127 kPXP_OutputField1, /*!< Only write field 1 data to output buffer 0. */
128 kPXP_OutputInterlaced, /*!< Field 0 write to buffer 0, field 1 write to buffer 1. */
129 } pxp_interlaced_output_mode_t;
130
131 /*! @brief PXP output buffer format. */
132 typedef enum _pxp_output_pixel_format
133 {
134 kPXP_OutputPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
135 kPXP_OutputPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
136 kPXP_OutputPixelFormatRGB888P = 0x5, /*!< 24-bit pixels without alpha (packed 24-bit format) */
137 kPXP_OutputPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
138 kPXP_OutputPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
139 kPXP_OutputPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
140 kPXP_OutputPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
141 kPXP_OutputPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
142 kPXP_OutputPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
143 kPXP_OutputPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
144 kPXP_OutputPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
145 kPXP_OutputPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
146 kPXP_OutputPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
147 kPXP_OutputPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
148 kPXP_OutputPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
149 kPXP_OutputPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
150 kPXP_OutputPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
151 } pxp_output_pixel_format_t;
152
153 /*! @brief PXP output buffer configuration. */
154 typedef struct _pxp_output_buffer_config
155 {
156 pxp_output_pixel_format_t pixelFormat; /*!< Output buffer pixel format. */
157 pxp_interlaced_output_mode_t interlacedMode; /*!< Interlaced output mode. */
158 uint32_t buffer0Addr; /*!< Output buffer 0 address. */
159 uint32_t buffer1Addr; /*!< Output buffer 1 address, used for UV data in YUV 2-plane mode, or
160 field 1 in output interlaced mode. */
161 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
162 uint16_t width; /*!< Pixels per line. */
163 uint16_t height; /*!< How many lines in output buffer. */
164 } pxp_output_buffer_config_t;
165
166 /*! @brief PXP process surface buffer pixel format. */
167 typedef enum _pxp_ps_pixel_format
168 {
169 kPXP_PsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
170 kPXP_PsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
171 kPXP_PsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
172 kPXP_PsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
173 kPXP_PsPixelFormatYUV1P444 = 0x10, /*!< 32-bit pixels (1-plane XYUV unpacked). */
174 kPXP_PsPixelFormatUYVY1P422 = 0x12, /*!< 16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes) */
175 kPXP_PsPixelFormatVYUY1P422 = 0x13, /*!< 16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes) */
176 kPXP_PsPixelFormatY8 = 0x14, /*!< 8-bit monochrome pixels (1-plane Y luma output) */
177 kPXP_PsPixelFormatY4 = 0x15, /*!< 4-bit monochrome pixels (1-plane Y luma, 4 bit truncation) */
178 kPXP_PsPixelFormatYUV2P422 = 0x18, /*!< 16-bit pixels (2-plane UV interleaved bytes) */
179 kPXP_PsPixelFormatYUV2P420 = 0x19, /*!< 16-bit pixels (2-plane UV) */
180 kPXP_PsPixelFormatYVU2P422 = 0x1A, /*!< 16-bit pixels (2-plane VU interleaved bytes) */
181 kPXP_PsPixelFormatYVU2P420 = 0x1B, /*!< 16-bit pixels (2-plane VU) */
182 kPXP_PsPixelFormatYVU422 = 0x1E, /*!< 16-bit pixels (3-plane) */
183 kPXP_PsPixelFormatYVU420 = 0x1F, /*!< 16-bit pixels (3-plane) */
184 } pxp_ps_pixel_format_t;
185
186 /*! @brief PXP process surface buffer YUV format. */
187 typedef enum _pxp_ps_yuv_format
188 {
189 kPXP_PsYUVFormatYUV = 0U, /*!< YUV format. */
190 kPXP_PsYUVFormatYCbCr, /*!< YCbCr format. */
191 } pxp_ps_yuv_format_t;
192
193 /*! @brief PXP process surface buffer configuration. */
194 typedef struct _pxp_ps_buffer_config
195 {
196 pxp_ps_pixel_format_t pixelFormat; /*!< PS buffer pixel format. */
197 bool swapByte; /*!< For each 16 bit word, set true to swap the two bytes. */
198 uint32_t bufferAddr; /*!< Input buffer address for the first panel. */
199 uint32_t bufferAddrU; /*!< Input buffer address for the second panel. */
200 uint32_t bufferAddrV; /*!< Input buffer address for the third panel. */
201 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
202 } pxp_ps_buffer_config_t;
203
204 /*! @brief PXP alpha surface buffer pixel format. */
205 typedef enum _pxp_as_pixel_format
206 {
207 kPXP_AsPixelFormatARGB8888 = 0x0, /*!< 32-bit pixels with alpha. */
208 kPXP_AsPixelFormatRGB888 = 0x4, /*!< 32-bit pixels without alpha (unpacked 24-bit format) */
209 kPXP_AsPixelFormatARGB1555 = 0x8, /*!< 16-bit pixels with alpha. */
210 kPXP_AsPixelFormatARGB4444 = 0x9, /*!< 16-bit pixels with alpha. */
211 kPXP_AsPixelFormatRGB555 = 0xC, /*!< 16-bit pixels without alpha. */
212 kPXP_AsPixelFormatRGB444 = 0xD, /*!< 16-bit pixels without alpha. */
213 kPXP_AsPixelFormatRGB565 = 0xE, /*!< 16-bit pixels without alpha. */
214 } pxp_as_pixel_format_t;
215
216 /*! @brief PXP alphs surface buffer configuration. */
217 typedef struct _pxp_as_buffer_config
218 {
219 pxp_as_pixel_format_t pixelFormat; /*!< AS buffer pixel format. */
220 uint32_t bufferAddr; /*!< Input buffer address. */
221 uint16_t pitchBytes; /*!< Number of bytes between two vertically adjacent pixels. */
222 } pxp_as_buffer_config_t;
223
224 /*!
225 * @brief PXP alpha mode during blending.
226 */
227 typedef enum _pxp_alpha_mode
228 {
229 kPXP_AlphaEmbedded, /*!< The alpha surface pixel alpha value will be used for blend. */
230 kPXP_AlphaOverride, /*!< The user defined alpha value will be used for blend directly. */
231 kPXP_AlphaMultiply, /*!< The alpha surface pixel alpha value scaled the user defined
232 alpha value will be used for blend, for example, pixel alpha set
233 set to 200, user defined alpha set to 100, then the reault alpha
234 is 200 * 100 / 255. */
235 kPXP_AlphaRop /*!< Raster operation. */
236 } pxp_alpha_mode_t;
237
238 /*!
239 * @brief PXP ROP mode during blending.
240 *
241 * Explanation:
242 * - AS: Alpha surface
243 * - PS: Process surface
244 * - nAS: Alpha surface NOT value
245 * - nPS: Process surface NOT value
246 */
247 typedef enum _pxp_rop_mode
248 {
249 kPXP_RopMaskAs = 0x0, /*!< AS AND PS. */
250 kPXP_RopMaskNotAs = 0x1, /*!< nAS AND PS. */
251 kPXP_RopMaskAsNot = 0x2, /*!< AS AND nPS. */
252 kPXP_RopMergeAs = 0x3, /*!< AS OR PS. */
253 kPXP_RopMergeNotAs = 0x4, /*!< nAS OR PS. */
254 kPXP_RopMergeAsNot = 0x5, /*!< AS OR nPS. */
255 kPXP_RopNotCopyAs = 0x6, /*!< nAS. */
256 kPXP_RopNot = 0x7, /*!< nPS. */
257 kPXP_RopNotMaskAs = 0x8, /*!< AS NAND PS. */
258 kPXP_RopNotMergeAs = 0x9, /*!< AS NOR PS. */
259 kPXP_RopXorAs = 0xA, /*!< AS XOR PS. */
260 kPXP_RopNotXorAs = 0xB /*!< AS XNOR PS. */
261 } pxp_rop_mode_t;
262
263 /*!
264 * @brief PXP alpha surface blending configuration.
265 */
266 typedef struct _pxp_as_blend_config
267 {
268 uint8_t alpha; /*!< User defined alpha value, only used when @ref alphaMode is @ref kPXP_AlphaOverride or @ref
269 kPXP_AlphaRop. */
270 bool invertAlpha; /*!< Set true to invert the alpha. */
271 pxp_alpha_mode_t alphaMode; /*!< Alpha mode. */
272 pxp_rop_mode_t ropMode; /*!< ROP mode, only valid when @ref alphaMode is @ref kPXP_AlphaRop. */
273 } pxp_as_blend_config_t;
274
275 /*! @brief PXP process block size. */
276 typedef enum _pxp_block_size
277 {
278 kPXP_BlockSize8 = 0U, /*!< Process 8x8 pixel blocks. */
279 kPXP_BlockSize16, /*!< Process 16x16 pixel blocks. */
280 } pxp_block_size_t;
281
282 /*! @brief PXP CSC1 mode. */
283 typedef enum _pxp_csc1_mode
284 {
285 kPXP_Csc1YUV2RGB = 0U, /*!< YUV to RGB. */
286 kPXP_Csc1YCbCr2RGB, /*!< YCbCr to RGB. */
287 } pxp_csc1_mode_t;
288
289 /*! @brief PXP CSC2 mode. */
290 typedef enum _pxp_csc2_mode
291 {
292 kPXP_Csc2YUV2RGB = 0U, /*!< YUV to RGB. */
293 kPXP_Csc2YCbCr2RGB, /*!< YCbCr to RGB. */
294 kPXP_Csc2RGB2YUV, /*!< RGB to YUV. */
295 kPXP_Csc2RGB2YCbCr, /*!< RGB to YCbCr. */
296 } pxp_csc2_mode_t;
297
298 /*!
299 * @brief PXP CSC2 configuration.
300 *
301 * Converting from YUV/YCbCr color spaces to the RGB color space uses the
302 * following equation structure:
303 *
304 * R = A1(Y+D1) + A2(U+D2) + A3(V+D3)
305 * G = B1(Y+D1) + B2(U+D2) + B3(V+D3)
306 * B = C1(Y+D1) + C2(U+D2) + C3(V+D3)
307 *
308 * Converting from the RGB color space to YUV/YCbCr color spaces uses the
309 * following equation structure:
310 *
311 * Y = A1*R + A2*G + A3*B + D1
312 * U = B1*R + B2*G + B3*B + D2
313 * V = C1*R + C2*G + C3*B + D3
314 */
315 typedef struct _pxp_csc2_config
316 {
317 pxp_csc2_mode_t mode; /*!< Convertion mode. */
318 float A1; /*!< A1. */
319 float A2; /*!< A2. */
320 float A3; /*!< A3. */
321 float B1; /*!< B1. */
322 float B2; /*!< B2. */
323 float B3; /*!< B3. */
324 float C1; /*!< C1. */
325 float C2; /*!< C2. */
326 float C3; /*!< C3. */
327 int16_t D1; /*!< D1. */
328 int16_t D2; /*!< D2. */
329 int16_t D3; /*!< D3. */
330 } pxp_csc2_config_t;
331
332 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
333 /*! @brief PXP LUT lookup mode. */
334 typedef enum _pxp_lut_lookup_mode
335 {
336 kPXP_LutCacheRGB565 = 0U, /*!< LUT ADDR = R[7:3],G[7:2],B[7:3]. Use all 16KB of LUT
337 for indirect cached 128KB lookup. */
338 kPXP_LutDirectY8, /*!< LUT ADDR = 16'b0,Y[7:0]. Use the first 256 bytes of LUT.
339 Only third data path byte is tranformed. */
340 kPXP_LutDirectRGB444, /*!< LUT ADDR = R[7:4],G[7:4],B[7:4]. Use one 8KB bank of LUT
341 selected by @ref PXP_Select8kLutBank. */
342 kPXP_LutDirectRGB454, /*!< LUT ADDR = R[7:4],G[7:3],B[7:4]. Use all 16KB of LUT. */
343 } pxp_lut_lookup_mode_t;
344
345 /*! @brief PXP LUT output mode. */
346 typedef enum _pxp_lut_out_mode
347 {
348 kPXP_LutOutY8 = 1U, /*!< R/Y byte lane 2 lookup, bytes 1,0 bypassed. */
349 kPXP_LutOutRGBW4444CFA, /*!< Byte lane 2 = CFA_Y8, byte lane 1,0 = RGBW4444. */
350 kPXP_LutOutRGB888, /*!< RGB565->RGB888 conversion for Gamma correction. */
351 } pxp_lut_out_mode_t;
352
353 /*! @brief PXP LUT 8K bank index used when lookup mode is @ref kPXP_LutDirectRGB444. */
354 typedef enum _pxp_lut_8k_bank
355 {
356 kPXP_Lut8kBank0 = 0U, /*!< The first 8K bank used. */
357 kPXP_Lut8kBank1, /*!< The second 8K bank used. */
358 } pxp_lut_8k_bank_t;
359
360 /*! @brief PXP LUT configuration. */
361 typedef struct _pxp_lut_config
362 {
363 pxp_lut_lookup_mode_t lookupMode; /*!< Look up mode. */
364 pxp_lut_out_mode_t outMode; /*!< Out mode. */
365 uint32_t cfaValue; /*!< The CFA value used when look up mode is @ref kPXP_LutOutRGBW4444CFA. */
366 } pxp_lut_config_t;
367 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
368
369 /*! @brief PXP internal memory. */
370 typedef enum _pxp_ram
371 {
372 kPXP_RamDither0Lut = 0U, /*!< Dither 0 LUT memory. */
373 kPXP_RamDither1Lut = 3U, /*!< Dither 1 LUT memory. */
374 kPXP_RamDither2Lut = 4U, /*!< Dither 2 LUT memory. */
375 } pxp_ram_t;
376
377 /*! @brief PXP dither mode. */
378 enum _pxp_dither_mode
379 {
380 kPXP_DitherPassThrough = 0U, /*!< Pass through, no dither. */
381 kPXP_DitherOrdered = 3U, /*!< Ordered dither. */
382 kPXP_DitherQuantOnly = 4U, /*!< No dithering, only quantization. */
383 };
384
385 /*! @brief PXP dither LUT mode. */
386 enum _pxp_dither_lut_mode
387 {
388 kPXP_DitherLutOff = 0U, /*!< The LUT memory is not used for LUT, could be used as ordered dither index matrix. */
389 kPXP_DitherLutPreDither, /*!< Use LUT at the pre-dither stage, The pre-dither LUT could only be used in Floyd mode
390 or Atkinson mode, which are not supported by current PXP module. */
391 kPXP_DitherLutPostDither, /*!< Use LUT at the post-dither stage. */
392 };
393
394 /*! @brief PXP dither matrix size. */
395 enum _pxp_dither_matrix_size
396 {
397 kPXP_DitherMatrix8 = 1, /*!< The dither index matrix is 8x8. */
398 kPXP_DitherMatrix16, /*!< The dither index matrix is 16x16. */
399 };
400
401 /*! @brief PXP dither final LUT data. */
402 typedef struct _pxp_dither_final_lut_data
403 {
404 uint32_t data_3_0; /*!< Data 3 to data 0. Data 0 is the least significant byte. */
405 uint32_t data_7_4; /*!< Data 7 to data 4. Data 4 is the least significant byte. */
406 uint32_t data_11_8; /*!< Data 11 to data 8. Data 8 is the least significant byte. */
407 uint32_t data_15_12; /*!< Data 15 to data 12. Data 12 is the least significant byte. */
408 } pxp_dither_final_lut_data_t;
409
410 /*! @brief PXP dither configuration. */
411 typedef struct _pxp_dither_config
412 {
413 uint32_t enableDither0 : 1; /*!< Enable dither engine 0 or not, set 1 to enable, 0 to disable. */
414 uint32_t enableDither1 : 1; /*!< Enable dither engine 1 or not, set 1 to enable, 0 to disable. */
415 uint32_t enableDither2 : 1; /*!< Enable dither engine 2 or not, set 1 to enable, 0 to disable. */
416 uint32_t ditherMode0 : 3; /*!< Dither mode for dither engine 0. See @ref _pxp_dither_mode. */
417 uint32_t ditherMode1 : 3; /*!< Dither mode for dither engine 1. See @ref _pxp_dither_mode. */
418 uint32_t ditherMode2 : 3; /*!< Dither mode for dither engine 2. See @ref _pxp_dither_mode. */
419 uint32_t quantBitNum : 3; /*!< Number of bits quantize down to, the valid value is 1~7. */
420 uint32_t lutMode : 2; /*!< How to use the memory LUT, see @ref _pxp_dither_lut_mode. This must be set to @ref
421 kPXP_DitherLutOff
422 if any dither engine uses @ref kPXP_DitherOrdered mode. */
423 uint32_t idxMatrixSize0 : 2; /*!< Size of index matrix used for dither for dither engine 0, see @ref
424 _pxp_dither_matrix_size. */
425 uint32_t idxMatrixSize1 : 2; /*!< Size of index matrix used for dither for dither engine 1, see @ref
426 _pxp_dither_matrix_size. */
427 uint32_t idxMatrixSize2 : 2; /*!< Size of index matrix used for dither for dither engine 2, see @ref
428 _pxp_dither_matrix_size. */
429 uint32_t enableFinalLut : 1; /*!< Enable the final LUT, set 1 to enable, 0 to disable. */
430 uint32_t : 8;
431 } pxp_dither_config_t;
432
433 /*!
434 * @brief Porter Duff factor mode.
435 * @anchor pxp_porter_duff_factor_mode
436 */
437 enum
438 {
439 kPXP_PorterDuffFactorOne = 0U, /*!< Use 1. */
440 kPXP_PorterDuffFactorZero, /*!< Use 0. */
441 kPXP_PorterDuffFactorStraight, /*!< Use straight alpha. */
442 kPXP_PorterDuffFactorInversed, /*!< Use inversed alpha. */
443 };
444
445 /*!
446 * @brief Porter Duff global alpha mode.
447 * @anchor pxp_porter_duff_global_alpha_mode
448 */
449 enum
450 {
451 kPXP_PorterDuffGlobalAlpha = 0U, /*!< Use global alpha. */
452 kPXP_PorterDuffLocalAlpha, /*!< Use local alpha in each pixel. */
453 kPXP_PorterDuffScaledAlpha, /*!< Use global alpha * local alpha. */
454 };
455
456 /*!
457 * @brief Porter Duff alpha mode.
458 * @anchor pxp_porter_duff_alpha_mode
459 */
460 enum
461 {
462 kPXP_PorterDuffAlphaStraight = 0U, /*!< Use straight alpha, s0_alpha' = s0_alpha. */
463 kPXP_PorterDuffAlphaInversed /*!< Use inversed alpha, s0_alpha' = 0xFF - s0_alpha. */
464 };
465
466 /*!
467 * @brief Porter Duff color mode.
468 * @anchor pxp_porter_duff_color_mode
469 */
470 enum
471 {
472 kPXP_PorterDuffColorStraight = 0, /*!< @deprecated Use kPXP_PorterDuffColorNoAlpha. */
473 kPXP_PorterDuffColorInversed = 1, /*!< @deprecated Use kPXP_PorterDuffColorWithAlpha. */
474 kPXP_PorterDuffColorNoAlpha = 0, /*!< s0_pixel' = s0_pixel. */
475 kPXP_PorterDuffColorWithAlpha = 1, /*!< s0_pixel' = s0_pixel * s0_alpha". */
476 };
477
478 /*! @brief PXP Porter Duff configuration. */
479 typedef struct
480 {
481 uint32_t enable : 1; /*!< Enable or disable Porter Duff. */
482 uint32_t srcFactorMode : 2; /*!< Source layer (or AS, s1) factor mode, see @ref pxp_porter_duff_factor_mode. */
483 uint32_t dstGlobalAlphaMode : 2; /*!< Destination layer (or PS, s0) global alpha mode, see
484 @ref pxp_porter_duff_global_alpha_mode. */
485 uint32_t dstAlphaMode : 1; /*!< Destination layer (or PS, s0) alpha mode, see @ref pxp_porter_duff_alpha_mode. */
486 uint32_t dstColorMode : 1; /*!< Destination layer (or PS, s0) color mode, see @ref pxp_porter_duff_color_mode. */
487 uint32_t : 1;
488 uint32_t dstFactorMode : 2; /*!< Destination layer (or PS, s0) factor mode, see @ref pxp_porter_duff_factor_mode. */
489 uint32_t srcGlobalAlphaMode : 2; /*!< Source layer (or AS, s1) global alpha mode, see
490 @ref pxp_porter_duff_global_alpha_mode. */
491 uint32_t srcAlphaMode : 1; /*!< Source layer (or AS, s1) alpha mode, see @ref pxp_porter_duff_alpha_mode. */
492 uint32_t srcColorMode : 1; /*!< Source layer (or AS, s1) color mode, see @ref pxp_porter_duff_color_mode. */
493 uint32_t : 2;
494 uint32_t dstGlobalAlpha : 8; /*!< Destination layer (or PS, s0) global alpha value, 0~255. */
495 uint32_t srcGlobalAlpha : 8; /*!< Source layer (or AS, s1) global alpha value, 0~255. */
496 } pxp_porter_duff_config_t;
497
498 /*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */
499 typedef enum _pxp_porter_duff_blend_mode
500 {
501 kPXP_PorterDuffSrc = 0, /*!< Source Only */
502 kPXP_PorterDuffAtop, /*!< Source Atop */
503 kPXP_PorterDuffOver, /*!< Source Over */
504 kPXP_PorterDuffIn, /*!< Source In. */
505 kPXP_PorterDuffOut, /*!< Source Out. */
506 kPXP_PorterDuffDst, /*!< Destination Only. */
507 kPXP_PorterDuffDstAtop, /*!< Destination Atop. */
508 kPXP_PorterDuffDstOver, /*!< Destination Over. */
509 kPXP_PorterDuffDstIn, /*!< Destination In. */
510 kPXP_PorterDuffDstOut, /*!< Destination Out. */
511 kPXP_PorterDuffXor, /*!< XOR. */
512 kPXP_PorterDuffClear, /*!< Clear. */
513 kPXP_PorterDuffMax,
514 } pxp_porter_duff_blend_mode_t;
515
516 /*! @brief PXP Porter Duff blend mode. Note: don't change the enum item value */
517 typedef struct _pxp_pic_copy_config
518 {
519 uint32_t srcPicBaseAddr; /*!< Source picture base address. */
520 uint16_t srcPitchBytes; /*!< Pitch of the source buffer. */
521 uint16_t srcOffsetX; /*!< Copy position in source picture. */
522 uint16_t srcOffsetY; /*!< Copy position in source picture. */
523 uint32_t destPicBaseAddr; /*!< Destination picture base address. */
524 uint16_t destPitchBytes; /*!< Pitch of the destination buffer. */
525 uint16_t destOffsetX; /*!< Copy position in destination picture. */
526 uint16_t destOffsetY; /*!< Copy position in destination picture. */
527 uint16_t width; /*!< Pixel number each line to copy. */
528 uint16_t height; /*!< Lines to copy. */
529 pxp_as_pixel_format_t pixelFormat; /*!< Buffer pixel format. */
530 } pxp_pic_copy_config_t;
531
532 /*******************************************************************************
533 * API
534 ******************************************************************************/
535
536 #if defined(__cplusplus)
537 extern "C" {
538 #endif
539
540 /*!
541 * @name Initialization and deinitialization
542 * @{
543 */
544
545 /*!
546 * @brief Initialize the PXP.
547 *
548 * This function enables the PXP peripheral clock, and resets the PXP registers
549 * to default status.
550 *
551 * @param base PXP peripheral base address.
552 */
553 void PXP_Init(PXP_Type *base);
554
555 /*!
556 * @brief De-initialize the PXP.
557 *
558 * This function disables the PXP peripheral clock.
559 *
560 * @param base PXP peripheral base address.
561 */
562 void PXP_Deinit(PXP_Type *base);
563
564 /*!
565 * @brief Reset the PXP.
566 *
567 * This function resets the PXP peripheral registers to default status.
568 *
569 * @param base PXP peripheral base address.
570 */
571 void PXP_Reset(PXP_Type *base);
572 /* @} */
573
574 /*!
575 * @name Global operations
576 * @{
577 */
578
579 /*!
580 * @brief Start process.
581 *
582 * Start PXP process using current configuration.
583 *
584 * @param base PXP peripheral base address.
585 */
PXP_Start(PXP_Type * base)586 static inline void PXP_Start(PXP_Type *base)
587 {
588 base->CTRL_SET = PXP_CTRL_ENABLE_MASK;
589 }
590
591 /*!
592 * @brief Enable or disable LCD hand shake.
593 *
594 * @param base PXP peripheral base address.
595 * @param enable True to enable, false to disable.
596 */
PXP_EnableLcdHandShake(PXP_Type * base,bool enable)597 static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable)
598 {
599 #if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
600 if (enable)
601 {
602 base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
603 }
604 else
605 {
606 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
607 }
608 #else
609 if (enable)
610 {
611 base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
612 }
613 else
614 {
615 base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
616 }
617 #endif
618 }
619
620 #if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT)
621 /*!
622 * @brief Enable or disable continous run.
623 *
624 * If continous run not enabled, @ref PXP_Start starts the PXP process. When completed,
625 * PXP enters idle mode and flag @ref kPXP_CompleteFlag asserts.
626 *
627 * If continous run enabled, the PXP will repeat based on the current configuration register
628 * settings.
629 *
630 * @param base PXP peripheral base address.
631 * @param enable True to enable, false to disable.
632 */
PXP_EnableContinousRun(PXP_Type * base,bool enable)633 static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable)
634 {
635 if (enable)
636 {
637 base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK;
638 }
639 else
640 {
641 base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK;
642 }
643 }
644 #endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */
645
646 /*!
647 * @brief Set the PXP processing block size
648 *
649 * This function chooses the pixel block size that PXP using during process.
650 * Larger block size means better performace, but be careful that when PXP is
651 * rotating, the output must be divisible by the block size selected.
652 *
653 * @param base PXP peripheral base address.
654 * @param size The pixel block size.
655 */
PXP_SetProcessBlockSize(PXP_Type * base,pxp_block_size_t size)656 static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size)
657 {
658 base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size);
659 }
660
661 /* @} */
662
663 /*!
664 * @name Status
665 * @{
666 */
667
668 /*!
669 * @brief Gets PXP status flags.
670 *
671 * This function gets all PXP status flags. The flags are returned as the logical
672 * OR value of the enumerators @ref _pxp_flags. To check a specific status,
673 * compare the return value with enumerators in @ref _pxp_flags.
674 * For example, to check whether the PXP has completed process, use like this:
675 * @code
676 if (kPXP_CompleteFlag & PXP_GetStatusFlags(PXP))
677 {
678 ...
679 }
680 @endcode
681 *
682 * @param base PXP peripheral base address.
683 * @return PXP status flags which are OR'ed by the enumerators in the _pxp_flags.
684 */
PXP_GetStatusFlags(PXP_Type * base)685 static inline uint32_t PXP_GetStatusFlags(PXP_Type *base)
686 {
687 #if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
688 return base->STAT &
689 (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
690 PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK | PXP_STAT_AXI_WRITE_ERROR_1_MASK);
691 #else
692 return base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
693 PXP_STAT_AXI_WRITE_ERROR_0_MASK);
694 #endif
695 }
696
697 /*!
698 * @brief Clears status flags with the provided mask.
699 *
700 * This function clears PXP status flags with a provided mask.
701 *
702 * @param base PXP peripheral base address.
703 * @param statusMask The status flags to be cleared; it is logical OR value of @ref _pxp_flags.
704 */
PXP_ClearStatusFlags(PXP_Type * base,uint32_t statusMask)705 static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask)
706 {
707 base->STAT_CLR = statusMask;
708 }
709
710 /*!
711 * @brief Gets the AXI ID of the failing bus operation.
712 *
713 * @param base PXP peripheral base address.
714 * @param axiIndex Whitch AXI to get
715 * - 0: AXI0
716 * - 1: AXI1
717 * @return The AXI ID of the failing bus operation.
718 */
PXP_GetAxiErrorId(PXP_Type * base,uint8_t axiIndex)719 static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)
720 {
721 #if defined(PXP_STAT_AXI_ERROR_ID_1_MASK)
722 if (0 == axiIndex)
723 {
724 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT);
725 }
726 else
727 {
728 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT);
729 }
730 #else
731 return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT);
732 #endif
733 }
734
735 /* @} */
736
737 /*!
738 * @name Interrupts
739 * @{
740 */
741
742 /*!
743 * @brief Enables PXP interrupts according to the provided mask.
744 *
745 * This function enables the PXP interrupts according to the provided mask. The mask
746 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable.
747 * For example, to enable PXP process complete interrupt and command loaded
748 * interrupt, do the following.
749 * @code
750 PXP_EnableInterrupts(PXP, kPXP_CommandLoadInterruptEnable | kPXP_CompleteInterruptEnable);
751 @endcode
752 *
753 * @param base PXP peripheral base address.
754 * @param mask The interrupts to enable. Logical OR of @ref _pxp_interrupt_enable.
755 */
PXP_EnableInterrupts(PXP_Type * base,uint32_t mask)756 static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask)
757 {
758 base->CTRL_SET = mask;
759 }
760
761 /*!
762 * @brief Disables PXP interrupts according to the provided mask.
763 *
764 * This function disables the PXP interrupts according to the provided mask. The mask
765 * is a logical OR of enumeration members. See @ref _pxp_interrupt_enable.
766 *
767 * @param base PXP peripheral base address.
768 * @param mask The interrupts to disable. Logical OR of @ref _pxp_interrupt_enable.
769 */
PXP_DisableInterrupts(PXP_Type * base,uint32_t mask)770 static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask)
771 {
772 base->CTRL_CLR = mask;
773 }
774
775 /* @} */
776
777 /*!
778 * @name Alpha surface
779 * @{
780 */
781
782 /*!
783 * @brief Set the alpha surface input buffer configuration.
784 *
785 * @param base PXP peripheral base address.
786 * @param config Pointer to the configuration.
787 */
788 void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config);
789
790 /*!
791 * @brief Set the alpha surface blending configuration.
792 *
793 * @param base PXP peripheral base address.
794 * @param config Pointer to the configuration structure.
795 */
796 void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config);
797
798 /*!
799 * @brief Set the alpha surface overlay color key.
800 *
801 * If a pixel in the current overlay image with a color that falls in the range
802 * from the @p colorKeyLow to @p colorKeyHigh range, it will use the process surface
803 * pixel value for that location. If no PS image is present or if the PS image also
804 * matches its colorkey range, the PS background color is used.
805 *
806 * @param base PXP peripheral base address.
807 * @param colorKeyLow Color key low range.
808 * @param colorKeyHigh Color key high range.
809 *
810 * @note Colorkey operations are higher priority than alpha or ROP operations
811 */
812 void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
813
814 /*!
815 * @brief Enable or disable the alpha surface color key.
816 *
817 * @param base PXP peripheral base address.
818 * @param enable True to enable, false to disable.
819 */
PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type * base,bool enable)820 static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable)
821 {
822 if (enable)
823 {
824 base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
825 }
826 else
827 {
828 base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
829 }
830 }
831
832 /*!
833 * @brief Set the alpha surface position in output buffer.
834 *
835 * @param base PXP peripheral base address.
836 * @param upperLeftX X of the upper left corner.
837 * @param upperLeftY Y of the upper left corner.
838 * @param lowerRightX X of the lower right corner.
839 * @param lowerRightY Y of the lower right corner.
840 */
841 void PXP_SetAlphaSurfacePosition(
842 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
843 /* @} */
844
845 /*!
846 * @name Process surface
847 * @{
848 */
849
850 /*!
851 * @brief Set the back ground color of PS.
852 *
853 * @param base PXP peripheral base address.
854 * @param backGroundColor Pixel value of the background color.
855 */
PXP_SetProcessSurfaceBackGroundColor(PXP_Type * base,uint32_t backGroundColor)856 static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor)
857 {
858 #if defined(PXP_PS_BACKGROUND_0_COLOR_MASK)
859 base->PS_BACKGROUND_0 = backGroundColor;
860 #else
861 base->PS_BACKGROUND = backGroundColor;
862 #endif
863 }
864
865 /*!
866 * @brief Set the process surface input buffer configuration.
867 *
868 * @param base PXP peripheral base address.
869 * @param config Pointer to the configuration.
870 */
871 void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config);
872
873 /*!
874 * @brief Set the process surface scaler configuration.
875 *
876 * The valid down scale fact is 1/(2^12) ~ 16.
877 *
878 * @param base PXP peripheral base address.
879 * @param inputWidth Input image width.
880 * @param inputHeight Input image height.
881 * @param outputWidth Output image width.
882 * @param outputHeight Output image height.
883 */
884 void PXP_SetProcessSurfaceScaler(
885 PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight);
886
887 /*!
888 * @brief Set the process surface position in output buffer.
889 *
890 * @param base PXP peripheral base address.
891 * @param upperLeftX X of the upper left corner.
892 * @param upperLeftY Y of the upper left corner.
893 * @param lowerRightX X of the lower right corner.
894 * @param lowerRightY Y of the lower right corner.
895 */
896 void PXP_SetProcessSurfacePosition(
897 PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
898
899 /*!
900 * @brief Set the process surface color key.
901 *
902 * If the PS image matches colorkey range, the PS background color is output. Set
903 * @p colorKeyLow to 0xFFFFFFFF and @p colorKeyHigh to 0 will disable the colorkeying.
904 *
905 * @param base PXP peripheral base address.
906 * @param colorKeyLow Color key low range.
907 * @param colorKeyHigh Color key high range.
908 */
909 void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
910
911 /*!
912 * @brief Set the process surface input pixel format YUV or YCbCr.
913 *
914 * If process surface input pixel format is YUV and CSC1 is not enabled,
915 * in other words, the process surface output pixel format is also YUV,
916 * then this function should be called to set whether input pixel format
917 * is YUV or YCbCr.
918 *
919 * @param base PXP peripheral base address.
920 * @param format The YUV format.
921 */
PXP_SetProcessSurfaceYUVFormat(PXP_Type * base,pxp_ps_yuv_format_t format)922 static inline void PXP_SetProcessSurfaceYUVFormat(PXP_Type *base, pxp_ps_yuv_format_t format)
923 {
924 if (kPXP_PsYUVFormatYUV == format)
925 {
926 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_YCBCR_MODE_MASK;
927 }
928 else
929 {
930 base->CSC1_COEF0 |= PXP_CSC1_COEF0_YCBCR_MODE_MASK;
931 }
932 }
933 /* @} */
934
935 /*!
936 * @name Output buffer
937 * @{
938 */
939
940 /*!
941 * @brief Set the PXP outpt buffer configuration.
942 *
943 * @param base PXP peripheral base address.
944 * @param config Pointer to the configuration.
945 */
946 void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config);
947
948 /*!
949 * @brief Set the global overwritten alpha value.
950 *
951 * If global overwritten alpha is enabled, the alpha component in output buffer pixels
952 * will be overwritten, otherwise the computed alpha value is used.
953 *
954 * @param base PXP peripheral base address.
955 * @param alpha The alpha value.
956 */
PXP_SetOverwrittenAlphaValue(PXP_Type * base,uint8_t alpha)957 static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha)
958 {
959 base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha);
960 }
961
962 /*!
963 * @brief Enable or disable the global overwritten alpha value.
964 *
965 * If global overwritten alpha is enabled, the alpha component in output buffer pixels
966 * will be overwritten, otherwise the computed alpha value is used.
967 *
968 * @param base PXP peripheral base address.
969 * @param enable True to enable, false to disable.
970 */
PXP_EnableOverWrittenAlpha(PXP_Type * base,bool enable)971 static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable)
972 {
973 if (enable)
974 {
975 base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
976 }
977 else
978 {
979 base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
980 }
981 }
982
983 /*!
984 * @brief Set the rotation configuration.
985 *
986 * The PXP could rotate the process surface or the output buffer. There are
987 * two PXP versions:
988 * - Version 1: Only has one rotate sub module, the output buffer and process
989 * surface share the same rotate sub module, which means the process surface
990 * and output buffer could not be rotate at the same time. When pass in
991 * @ref kPXP_RotateOutputBuffer, the process surface could not use the rotate,
992 * Also when pass in @ref kPXP_RotateProcessSurface, output buffer could not
993 * use the rotate.
994 * - Version 2: Has two seperate rotate sub modules, the output buffer and
995 * process surface could configure the rotation independently.
996 *
997 * Upper layer could use the macro PXP_SHARE_ROTATE to check which version is.
998 * PXP_SHARE_ROTATE=1 means version 1.
999 *
1000 * @param base PXP peripheral base address.
1001 * @param position Rotate process surface or output buffer.
1002 * @param degree Rotate degree.
1003 * @param flipMode Flip mode.
1004 *
1005 * @note This function is different depends on the macro PXP_SHARE_ROTATE.
1006 */
PXP_SetRotateConfig(PXP_Type * base,pxp_rotate_position_t position,pxp_rotate_degree_t degree,pxp_flip_mode_t flipMode)1007 static inline void PXP_SetRotateConfig(PXP_Type *base,
1008 pxp_rotate_position_t position,
1009 pxp_rotate_degree_t degree,
1010 pxp_flip_mode_t flipMode)
1011 {
1012 #if PXP_SHARE_ROTATE
1013 base->CTRL =
1014 (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) |
1015 PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT);
1016 #else
1017 uint32_t ctrl = base->CTRL;
1018
1019 if (kPXP_RotateOutputBuffer == position)
1020 {
1021 if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable))
1022 {
1023 base->DATA_PATH_CTRL0 =
1024 (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(0);
1025 }
1026 else
1027 {
1028 base->DATA_PATH_CTRL0 =
1029 (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX12_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX12_SEL(1);
1030 }
1031 ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK);
1032 ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT));
1033 }
1034 else
1035 {
1036 if ((degree != kPXP_Rotate0) || (flipMode != kPXP_FlipDisable))
1037 {
1038 base->DATA_PATH_CTRL0 =
1039 (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(1);
1040 }
1041 else
1042 {
1043 base->DATA_PATH_CTRL0 =
1044 (base->DATA_PATH_CTRL0 & (~PXP_DATA_PATH_CTRL0_MUX3_SEL_MASK)) | PXP_DATA_PATH_CTRL0_MUX3_SEL(0);
1045 }
1046 ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK);
1047 ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT));
1048 }
1049
1050 base->CTRL = ctrl;
1051 #endif
1052 }
1053 /* @} */
1054
1055 /*!
1056 * @name Command queue
1057 * @{
1058 */
1059
1060 /*!
1061 * @brief Set the next command.
1062 *
1063 * The PXP supports a primitive ability to queue up one operation while the current
1064 * operation is running. Workflow:
1065 *
1066 * 1. Prepare the PXP register values except STAT, CSCCOEFn, NEXT in the memory
1067 * in the order they appear in the register map.
1068 * 2. Call this function sets the new operation to PXP.
1069 * 3. There are two methods to check whether the PXP has loaded the new operation.
1070 * The first method is using @ref PXP_IsNextCommandPending. If there is new operation
1071 * not loaded by the PXP, this function returns true. The second method is checking
1072 * the flag @ref kPXP_CommandLoadFlag, if command loaded, this flag asserts. User
1073 * could enable interrupt @ref kPXP_CommandLoadInterruptEnable to get the loaded
1074 * signal in interrupt way.
1075 * 4. When command loaded by PXP, a new command could be set using this function.
1076 *
1077 * @code
1078 uint32_t pxp_command1[48];
1079 uint32_t pxp_command2[48];
1080
1081 pxp_command1[0] = ...;
1082 pxp_command1[1] = ...;
1083 ...
1084 pxp_command2[0] = ...;
1085 pxp_command2[1] = ...;
1086 ...
1087
1088 while (PXP_IsNextCommandPending(PXP))
1089 {
1090 }
1091
1092 PXP_SetNextCommand(PXP, pxp_command1);
1093
1094 while (PXP_IsNextCommandPending(PXP))
1095 {
1096 }
1097
1098 PXP_SetNextCommand(PXP, pxp_command2);
1099 @endcode
1100 *
1101 * @param base PXP peripheral base address.
1102 * @param commandAddr Address of the new command.
1103 */
1104 void PXP_SetNextCommand(PXP_Type *base, void *commandAddr);
1105
1106 /*!
1107 * @brief Check whether the next command is pending.
1108 *
1109 * @param base UART peripheral base address.
1110 * @return True is pending, false is not.
1111 */
PXP_IsNextCommandPending(PXP_Type * base)1112 static inline bool PXP_IsNextCommandPending(PXP_Type *base)
1113 {
1114 return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK);
1115 }
1116
1117 /*!
1118 * @brief Cancel command set by @ref PXP_SetNextCommand
1119 *
1120 * @param base UART peripheral base address.
1121 */
PXP_CancelNextCommand(PXP_Type * base)1122 static inline void PXP_CancelNextCommand(PXP_Type *base)
1123 {
1124 /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */
1125 *((volatile uint32_t *)(&(base->NEXT)) + 2U) = PXP_NEXT_ENABLED_MASK;
1126 }
1127
1128 /* @} */
1129
1130 /*!
1131 * @name Color space conversion
1132 * @{
1133 */
1134
1135 #if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2)
1136 /*!
1137 * @brief Set the CSC2 configuration.
1138 *
1139 * The CSC2 module receives pixels in any color space and can convert the pixels
1140 * into any of RGB, YUV, or YCbCr color spaces. The output pixels are passed
1141 * onto the LUT and rotation engine for further processing
1142 *
1143 * @param base PXP peripheral base address.
1144 * @param config Pointer to the configuration.
1145 */
1146 void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config);
1147
1148 /*!
1149 * @brief Enable or disable the CSC2.
1150 *
1151 * @param base PXP peripheral base address.
1152 * @param enable True to enable, false to disable.
1153 */
PXP_EnableCsc2(PXP_Type * base,bool enable)1154 static inline void PXP_EnableCsc2(PXP_Type *base, bool enable)
1155 {
1156 if (enable)
1157 {
1158 base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK;
1159 }
1160 else
1161 {
1162 base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK;
1163 }
1164 }
1165 #endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */
1166
1167 /*!
1168 * @brief Set the CSC1 mode.
1169 *
1170 * The CSC1 module receives scaled YUV/YCbCr444 pixels from the scale engine and
1171 * converts the pixels to the RGB888 color space. It could only be used by process
1172 * surface.
1173 *
1174 * @param base PXP peripheral base address.
1175 * @param mode The conversion mode.
1176 */
1177 void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode);
1178
1179 /*!
1180 * @brief Enable or disable the CSC1.
1181 *
1182 * @param base PXP peripheral base address.
1183 * @param enable True to enable, false to disable.
1184 */
PXP_EnableCsc1(PXP_Type * base,bool enable)1185 static inline void PXP_EnableCsc1(PXP_Type *base, bool enable)
1186 {
1187 if (enable)
1188 {
1189 base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK;
1190 }
1191 else
1192 {
1193 base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK;
1194 }
1195 }
1196 /* @} */
1197
1198 #if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
1199 /*!
1200 * @name LUT operations
1201 * @{
1202 */
1203
1204 /*!
1205 * @brief Set the LUT configuration.
1206 *
1207 * The lookup table (LUT) is used to modify pixels in a manner that is not linear
1208 * and that cannot be achieved by the color space conversion modules. To setup
1209 * the LUT, the complete workflow is:
1210 * 1. Use @ref PXP_SetLutConfig to set the configuration, such as the lookup mode.
1211 * 2. Use @ref PXP_LoadLutTable to load the lookup table to PXP.
1212 * 3. Use @ref PXP_EnableLut to enable the function.
1213 *
1214 * @param base PXP peripheral base address.
1215 * @param config Pointer to the configuration.
1216 */
1217 void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config);
1218
1219 /*!
1220 * @brief Set the look up table to PXP.
1221 *
1222 * If lookup mode is DIRECT mode, this function loads @p bytesNum of values
1223 * from the address @p memAddr into PXP LUT address @p lutStartAddr. So this
1224 * function allows only update part of the PXP LUT.
1225 *
1226 * If lookup mode is CACHE mode, this function sets the new address to @p memAddr
1227 * and invalid the PXP LUT cache.
1228 *
1229 * @param base PXP peripheral base address.
1230 * @param lookupMode Which lookup mode is used. Note that this parameter is only
1231 * used to distinguish DIRECT mode and CACHE mode, it does not change the register
1232 * value PXP_LUT_CTRL[LOOKUP_MODE]. To change that value, use function @ref PXP_SetLutConfig.
1233 * @param bytesNum How many bytes to set. This value must be divisable by 8.
1234 * @param memAddr Address of look up table to set.
1235 * @param lutStartAddr The LUT value will be loaded to LUT from index lutAddr. It should
1236 * be 8 bytes aligned.
1237 *
1238 * @retval kStatus_Success Load successfully.
1239 * @retval kStatus_InvalidArgument Failed because of invalid argument.
1240 */
1241 status_t PXP_LoadLutTable(
1242 PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr);
1243
1244 /*!
1245 * @brief Enable or disable the LUT.
1246 *
1247 * @param base PXP peripheral base address.
1248 * @param enable True to enable, false to disable.
1249 */
PXP_EnableLut(PXP_Type * base,bool enable)1250 static inline void PXP_EnableLut(PXP_Type *base, bool enable)
1251 {
1252 if (enable)
1253 {
1254 base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK;
1255 }
1256 else
1257 {
1258 base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK;
1259 }
1260 }
1261
1262 /*!
1263 * @brief Select the 8kB LUT bank in DIRECT_RGB444 mode.
1264 *
1265 * @param base PXP peripheral base address.
1266 * @param bank The bank to select.
1267 */
PXP_Select8kLutBank(PXP_Type * base,pxp_lut_8k_bank_t bank)1268 static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank)
1269 {
1270 base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank);
1271 }
1272 /* @} */
1273 #endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
1274
1275 #if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER)
1276 /*!
1277 * @name Dither
1278 * @{
1279 */
1280
1281 /*!
1282 * @brief Write data to the PXP internal memory.
1283 *
1284 * @param base PXP peripheral base address.
1285 * @param ram Which internal memory to write.
1286 * @param bytesNum How many bytes to write.
1287 * @param data Pointer to the data to write.
1288 * @param memStartAddr The start address in the internal memory to write the data.
1289 */
1290 void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr);
1291
1292 /*!
1293 * @brief Set the dither final LUT data.
1294 *
1295 * The dither final LUT is only applicble to dither engine 0. It takes the bits[7:4]
1296 * of the output pixel and looks up and 8 bit value from the 16 value LUT to generate
1297 * the final output pixel to the next process module.
1298 *
1299 * @param base PXP peripheral base address.
1300 * @param data Pointer to the LUT data to set.
1301 */
1302 void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data);
1303
1304 /*!
1305 * @brief Set the configuration for the dither block.
1306 *
1307 * If the pre-dither LUT, post-dither LUT or ordered dither is used, please call
1308 * @ref PXP_SetInternalRamData to set the LUT data to internal memory.
1309 *
1310 * If the final LUT is used, please call @ref PXP_SetDitherFinalLutData to set
1311 * the LUT data.
1312 *
1313 * @param base PXP peripheral base address.
1314 * @param config Pointer to the configuration.
1315 *
1316 * @note When using ordered dithering, please set the PXP process block size same
1317 * with the ordered dithering matrix size using function @ref PXP_SetProcessBlockSize.
1318 */
PXP_SetDitherConfig(PXP_Type * base,const pxp_dither_config_t * config)1319 static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config)
1320 {
1321 base->DITHER_CTRL = *((const uint32_t *)config) & 0x00FFFFFFU;
1322 }
1323
1324 /*!
1325 * @brief Enable or disable dither engine in the PXP process path.
1326 *
1327 * After the initialize function @ref PXP_Init, the dither engine is disabled and not
1328 * use in the PXP processing path. This function enables the dither engine and
1329 * routes the dither engine output to the output buffer. When the dither engine
1330 * is enabled using this function, @ref PXP_SetDitherConfig must be called to
1331 * configure dither engine correctly, otherwise there is not output to the output
1332 * buffer.
1333 *
1334 * @param base PXP peripheral base address.
1335 * @param enable Pass in true to enable, false to disable.
1336 */
1337 void PXP_EnableDither(PXP_Type *base, bool enable);
1338
1339 /* @} */
1340
1341 #endif /* FSL_FEATURE_PXP_HAS_DITHER */
1342
1343 /*!
1344 * @name Porter Duff
1345 * @{
1346 */
1347
1348 /*!
1349 * @brief Set the Porter Duff configuration.
1350 *
1351 * @param base PXP peripheral base address.
1352 * @param config Pointer to the configuration.
1353 */
1354 void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *config);
1355
1356 /*!
1357 * @brief Get the Porter Duff configuration by blend mode.
1358 *
1359 * The FactorMode are selected based on blend mode, the AlphaMode are set to
1360 * @ref kPXP_PorterDuffAlphaStraight, the ColorMode are set to
1361 * @ref kPXP_PorterDuffColorWithAlpha, the GlobalAlphaMode are set to
1362 * @ref kPXP_PorterDuffLocalAlpha. These values could be modified after calling
1363 * this function.
1364 *
1365 * @param mode The blend mode.
1366 * @param config Pointer to the configuration.
1367 * @retval kStatus_Success Successfully get the configuratoin.
1368 * @retval kStatus_InvalidArgument The blend mode not supported.
1369 */
1370 status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config);
1371
1372 /* @} */
1373
1374 /*!
1375 * @name Buffer copy
1376 * @{
1377 */
1378
1379 /*!
1380 * @brief Copy picture from one buffer to another buffer.
1381 *
1382 * This function copies a rectangle from one buffer to another buffer.
1383 *
1384 * @verbatim
1385 Source buffer:
1386 srcPicBaseAddr
1387 +-----------------------------------------------------------+
1388 | |
1389 | (srcOffsetX, srcOffsetY) |
1390 | +-------------------+ |
1391 | | | |
1392 | | | |
1393 | | | height |
1394 | | | |
1395 | | | |
1396 | +-------------------+ |
1397 | width |
1398 | |
1399 | srcPicthBytes |
1400 +-----------------------------------------------------------+
1401
1402 Destination buffer:
1403 destPicBaseAddr
1404 +-------------------------------------------+
1405 | |
1406 | |
1407 | |
1408 | (destOffsetX, destOffsetY) |
1409 | +-------------------+ |
1410 | | | |
1411 | | | |
1412 | | | height |
1413 | | | |
1414 | | | |
1415 | +-------------------+ |
1416 | width |
1417 | |
1418 | |
1419 | |
1420 | destPicthBytes |
1421 +-------------------------------------------+
1422 @endverbatim
1423 *
1424 * @note This function resets the old PXP settings, which means the settings
1425 * like rotate, flip, will be reseted to disabled status.
1426 *
1427 * @param base PXP peripheral base address.
1428 * @param config Pointer to the picture copy configuration structure.
1429 * @retval kStatus_Success Successfully started the copy process.
1430 * @retval kStatus_InvalidArgument Invalid argument.
1431 */
1432 status_t PXP_StartPictureCopy(PXP_Type *base, const pxp_pic_copy_config_t *config);
1433
1434 /*!
1435 * @brief Copy continous memory.
1436 *
1437 * @note The copy size should be 512 byte aligned.
1438 * @note This function resets the old PXP settings, which means the settings
1439 * like rotate, flip, will be reseted to disabled status.
1440 *
1441 * @param base PXP peripheral base address.
1442 * @param srcAddr Source memory address.
1443 * @param destAddr Destination memory address.
1444 * @param size How many bytes to copy, should be 512 byte aligned.
1445 * @retval kStatus_Success Successfully started the copy process.
1446 * @retval kStatus_InvalidArgument Invalid argument.
1447 */
1448 status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size);
1449
1450 /* @} */
1451
1452 #if defined(__cplusplus)
1453 }
1454 #endif
1455
1456 /*! @}*/
1457
1458 #endif /* _FSL_PXP_H_ */
1459
