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Searched refs:XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h30961 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
30963 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h33890 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
33892 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h46034 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
46036 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h46016 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
46018 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h42150 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
42152 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h51968 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
51970 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h44558 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
44560 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h54627 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
54629 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h54553 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK (0x400U) macro
54555 …)) << XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h39981 #define XTALOSC24M_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u macro