Home
last modified time | relevance | path

Searched refs:XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h31029 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
31031 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h33958 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
33960 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h46116 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
46118 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h46098 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
46100 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h42218 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
42220 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h52050 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
52052 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h44626 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
44628 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h54709 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
54711 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h54635 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK (0x400U) macro
54637 …)) << XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT)) & XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK)
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h40014 #define XTALOSC24M_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u macro