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Searched refs:USBPHY_DEBUG_RSVD0_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h28577 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
28579 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h31375 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
31377 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h41263 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
41265 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h41245 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
41247 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h37945 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
37947 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h47149 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
47151 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h40353 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
40355 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h49808 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
49810 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h49734 #define USBPHY_DEBUG_RSVD0_MASK (0xC0U) macro
49736 … (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_RSVD0_SHIFT)) & USBPHY_DEBUG_RSVD0_MASK)
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h38462 #define USBPHY_DEBUG_RSVD0_MASK 0xC0u macro
38464 … (((uint32_t)(((uint32_t)(x))<<USBPHY_DEBUG_RSVD0_SHIFT))&USBPHY_DEBUG_RSVD0_MASK)