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Searched refs:USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h28805 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
28807 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h28699 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
28701 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h31497 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
31499 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h41423 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
41425 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h41405 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
41407 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h38067 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
38069 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h47309 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
47311 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h40475 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
40477 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h49968 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
49970 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h49894 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
49896 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
DMIMXRT1176_cm7.h96392 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
96396 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
DMIMXRT1176_cm4.h97323 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) macro
97327 …t32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h38562 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK 0x20000000u macro