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Searched refs:USBPHY1 (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
Dfsl_clock.c1644 USBPHY1->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
1646 USBPHY1->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); in CLOCK_EnableUsbhs0PhyPllClock()
1707 USBPHY1->PLL_SIC = (USBPHY1->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; in CLOCK_EnableUsbhs0PhyPllClock()
1709 USBPHY1->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
1710 USBPHY1->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_EnableUsbhs0PhyPllClock()
1712 USBPHY1->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
1713 USBPHY1->PWD_SET = 0x0; in CLOCK_EnableUsbhs0PhyPllClock()
1715 while (0UL == (USBPHY1->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) in CLOCK_EnableUsbhs0PhyPllClock()
1737 USBPHY1->PLL_SIC_CLR = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); in CLOCK_DisableUsbhs0PhyPllClock()
1738 USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
DMIMXRT1176_cm7.h98230 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
98238 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
DMIMXRT1176_cm4.h99161 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
99169 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
Dfsl_clock.c465 USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
466 USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
468 USBPHY1->PWD = 0; in CLOCK_EnableUsbhs0PhyPllClock()
469 USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs0PhyPllClock()
481 USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
DMIMXRT1051.h38215 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
38223 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
Dfsl_clock.c473 USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
474 USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
476 USBPHY1->PWD = 0; in CLOCK_EnableUsbhs0PhyPllClock()
477 USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs0PhyPllClock()
489 USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
DMIMXRT1061.h40623 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
40631 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
Dfsl_clock.c551 USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
552 USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
554 USBPHY1->PWD = 0; in CLOCK_EnableUsbhs0PhyPllClock()
555 USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs0PhyPllClock()
567 USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
DMIMXRT1052.h47492 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
47500 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
Dfsl_clock.c555 USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
556 USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
558 USBPHY1->PWD = 0; in CLOCK_EnableUsbhs0PhyPllClock()
559 USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs0PhyPllClock()
571 USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
DMIMXRT1062.h50151 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
50159 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
Dfsl_clock.c555 USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */ in CLOCK_EnableUsbhs0PhyPllClock()
556 USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK; in CLOCK_EnableUsbhs0PhyPllClock()
558 USBPHY1->PWD = 0; in CLOCK_EnableUsbhs0PhyPllClock()
559 USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | in CLOCK_EnableUsbhs0PhyPllClock()
571 USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ in CLOCK_DisableUsbhs0PhyPllClock()
DMIMXRT1064.h50077 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
50085 #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/hal_nxp-2.7.6/imx/devices/MCIMX6X/
DMCIMX6X_M4.h38676 #define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE) macro
38677 #define USBPHY1_BASE_PTR (USBPHY1)
38686 #define USBPHY_BASE_PTRS { USBPHY1, USBPHY2 }