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Searched refs:TX_DIG_EN_TX_HI_ADJ (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/
Dfsl_xcvr.h316 #define TX_DIG_EN_TX_HI_ADJ (-2) macro
319 #define TX_DIG_EN_TX_HI_ADJ (0) macro
329 #define TX_DIG_EN_TX_HI_ADJ (0) macro
340 #define TX_DIG_EN_TX_HI_ADJ (4) macro
/hal_nxp-2.7.6/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/
Dfsl_xcvr_ant_config.c110 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_ble_config.c106 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_gfsk_bt_0p3_h_0p5_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_gfsk_bt_0p5_h_0p32_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_gfsk_bt_0p5_h_0p7_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_gfsk_bt_0p5_h_1p0_config.c91 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_gfsk_bt_0p7_h_0p5_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_msk_config.c92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),
Dfsl_xcvr_gfsk_bt_0p5_h_0p5_config.c105 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ),