Home
last modified time | relevance | path

Searched refs:TCTRL (Results 1 – 25 of 46) sorted by relevance

12

/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_pit.h134 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
138 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
161 base->CHANNEL[channel].TCTRL |= mask; in PIT_EnableInterrupts()
174 base->CHANNEL[channel].TCTRL &= ~mask; in PIT_DisableInterrupts()
188 return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); in PIT_GetEnabledInterrupts()
290 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; in PIT_StartTimer()
304 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; in PIT_StopTimer()
Dfsl_pwm.h810 base->SM[subModule].TCTRL |= ((uint16_t)1U << (uint16_t)valueRegister); in PWM_OutputTriggerEnable()
814 base->SM[subModule].TCTRL &= ~((uint16_t)1U << (uint16_t)valueRegister); in PWM_OutputTriggerEnable()
830 base->SM[subModule].TCTRL |= (PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); in PWM_ActivateOutputTrigger()
845 base->SM[subModule].TCTRL &= ~(PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); in PWM_DeactivateOutputTrigger()
Dfsl_lpadc.c308 base->TCTRL[triggerId] = tmp32; in LPADC_SetConvTriggerConfig()
527 mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ in LPADC_DoAutoCalibration()
552 base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ in LPADC_DoAutoCalibration()
Dfsl_pit.c86 base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK); in PIT_Init()
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_pit.h134 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
138 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
161 base->CHANNEL[channel].TCTRL |= mask; in PIT_EnableInterrupts()
174 base->CHANNEL[channel].TCTRL &= ~mask; in PIT_DisableInterrupts()
188 return (base->CHANNEL[channel].TCTRL & PIT_TCTRL_TIE_MASK); in PIT_GetEnabledInterrupts()
290 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; in PIT_StartTimer()
304 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; in PIT_StopTimer()
Dfsl_pwm.h810 base->SM[subModule].TCTRL |= ((uint16_t)1U << (uint16_t)valueRegister); in PWM_OutputTriggerEnable()
814 base->SM[subModule].TCTRL &= ~((uint16_t)1U << (uint16_t)valueRegister); in PWM_OutputTriggerEnable()
830 base->SM[subModule].TCTRL |= (PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); in PWM_ActivateOutputTrigger()
845 base->SM[subModule].TCTRL &= ~(PWM_TCTRL_OUT_TRIG_EN_MASK & (valueRegisterMask)); in PWM_DeactivateOutputTrigger()
Dfsl_pit.c86 base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK); in PIT_Init()
Dfsl_lpit.c180 base->CHANNEL[channel].TCTRL = reg; in LPIT_SetupChannel()
/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_lpadc.c308 base->TCTRL[triggerId] = tmp32; in LPADC_SetConvTriggerConfig()
527 mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ in LPADC_DoAutoCalibration()
552 base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ in LPADC_DoAutoCalibration()
/hal_nxp-2.7.6/mcux/drivers/lpc/
Dfsl_lpadc.c308 base->TCTRL[triggerId] = tmp32; in LPADC_SetConvTriggerConfig()
527 mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */ in LPADC_DoAutoCalibration()
552 base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */ in LPADC_DoAutoCalibration()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h2925 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h5434 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
5457 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h5434 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
5457 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h5434 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
5457 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h16483 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
17074 …__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offse… member
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h17823 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
18414 …__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offse… member
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h9896 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h5456 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h8361 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, … member
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h5456 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h9165 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, … member
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h9170 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x28, … member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h19290 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
21362 …__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offse… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h21651 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member
23699 …__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offse… member
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h5138 …__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108,… member

12