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Searched refs:SYSCON_PLL0SSCG1_MF_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/LPC55S28/
DLPC55S28.h23312 #define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) macro
23316 … (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)
/hal_nxp-2.7.6/mcux/devices/LPC55S69/
DLPC55S69_cm33_core0.h23932 #define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) macro
23936 … (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)
DLPC55S69_cm33_core1.h23932 #define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) macro
23936 … (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)
/hal_nxp-2.7.6/mcux/devices/LPC55S16/
DLPC55S16.h23190 #define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) macro
23194 … (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK)