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Searched refs:SNVS_HPSVSR_SV5_MASK (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_snvs_hp.h61 #ifndef SNVS_HPSVSR_SV5_MASK
62 #define SNVS_HPSVSR_SV5_MASK SNVS_HPSVSR_OCOTP_MASK macro
81 kSNVS_Violation5Flag = SNVS_HPSVSR_SV5_MASK, /*!< Security Violation 5 */
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h23855 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
23861 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h26175 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
26181 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h35256 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
35262 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h35238 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
35244 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h32288 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
32294 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h40631 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
40637 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h34693 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
34699 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h43287 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
43293 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h43213 #define SNVS_HPSVSR_SV5_MASK (0x20U) macro
43219 … (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK)