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Searched refs:SIM_SCGC6_TPM1_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h3840 #define SIM_SCGC6_TPM1_MASK (0x2000000U) macro
3842 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h6471 #define SIM_SCGC6_TPM1_MASK (0x2000000U) macro
6473 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h7044 #define SIM_SCGC6_TPM1_MASK 0x2000000u macro
7047 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM1_SHIFT))&SIM_SCGC6_TPM1_MASK)
DMKW40Z4_extension.h20385 #define SIM_RD_SCGC6_TPM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM1_MASK) >> SIM_SCGC6_TPM1_SHIF…
20389 #define SIM_WR_SCGC6_TPM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM1_MASK, SIM_SCGC6_TPM1(val…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h6400 #define SIM_SCGC6_TPM1_MASK (0x2000000U) macro
6402 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h6471 #define SIM_SCGC6_TPM1_MASK (0x2000000U) macro
6473 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h7044 #define SIM_SCGC6_TPM1_MASK 0x2000000u macro
7047 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM1_SHIFT))&SIM_SCGC6_TPM1_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h7044 #define SIM_SCGC6_TPM1_MASK 0x2000000u macro
7047 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM1_SHIFT))&SIM_SCGC6_TPM1_MASK)