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Searched refs:SIM_SCGC6_TPM0_MASK (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h3837 #define SIM_SCGC6_TPM0_MASK (0x1000000U) macro
3839 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h6468 #define SIM_SCGC6_TPM0_MASK (0x1000000U) macro
6470 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h7040 #define SIM_SCGC6_TPM0_MASK 0x1000000u macro
7043 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM0_SHIFT))&SIM_SCGC6_TPM0_MASK)
DMKW40Z4_extension.h20366 #define SIM_RD_SCGC6_TPM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM0_MASK) >> SIM_SCGC6_TPM0_SHIF…
20370 #define SIM_WR_SCGC6_TPM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM0_MASK, SIM_SCGC6_TPM0(val…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h6397 #define SIM_SCGC6_TPM0_MASK (0x1000000U) macro
6399 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h6468 #define SIM_SCGC6_TPM0_MASK (0x1000000U) macro
6470 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h7040 #define SIM_SCGC6_TPM0_MASK 0x1000000u macro
7043 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM0_SHIFT))&SIM_SCGC6_TPM0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h7040 #define SIM_SCGC6_TPM0_MASK 0x1000000u macro
7043 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_TPM0_SHIFT))&SIM_SCGC6_TPM0_MASK)