Searched refs:SIM_SCGC6_FTF_MASK (Results 1 – 15 of 15) sorted by relevance
3828 #define SIM_SCGC6_FTF_MASK (0x1U) macro3830 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
12170 #define SIM_SCGC6_FTF_MASK (0x1U) macro12176 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
6450 #define SIM_SCGC6_FTF_MASK (0x1U) macro6452 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
21827 #define SIM_SCGC6_FTF_MASK (0x1U) macro21833 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
7016 #define SIM_SCGC6_FTF_MASK 0x1u macro7019 …(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_FTF_SHIFT))&SIM_SCGC6_FTF_MASK)
20252 #define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)20256 #define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)…
6379 #define SIM_SCGC6_FTF_MASK (0x1U) macro6381 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
19832 #define SIM_SCGC6_FTF_MASK (0x1U) macro19838 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
22288 #define SIM_SCGC6_FTF_MASK (0x1U) macro22294 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
21172 #define SIM_SCGC6_FTF_MASK (0x1U) macro21178 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
23268 #define SIM_SCGC6_FTF_MASK (0x1U) macro23274 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
22402 #define SIM_SCGC6_FTF_MASK (0x1U) macro22408 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
