Searched refs:SIM_SCGC6_ADC0_MASK (Results 1 – 17 of 17) sorted by relevance
3846 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro3848 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
12278 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro12284 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
6652 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro6654 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
6477 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro6479 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
21937 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro21943 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
7052 #define SIM_SCGC6_ADC0_MASK 0x8000000u macro7055 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC6_ADC0_SHIFT))&SIM_SCGC6_ADC0_MASK)
20423 #define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIF…20427 #define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(val…
6406 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro6408 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
19930 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro19936 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
22372 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro22378 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
21270 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro21276 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
23352 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro23358 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
22496 #define SIM_SCGC6_ADC0_MASK (0x8000000U) macro22502 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
