Searched refs:SIM_SCGC5_TSI_MASK (Results 1 – 11 of 11) sorted by relevance
3808 #define SIM_SCGC5_TSI_MASK (0x20U) macro3810 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
6409 #define SIM_SCGC5_TSI_MASK (0x20U) macro6411 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
6971 #define SIM_SCGC5_TSI_MASK 0x20u macro6974 …(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_TSI_SHIFT))&SIM_SCGC5_TSI_MASK)
20023 #define SIM_RD_SCGC5_TSI(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_TSI_MASK) >> SIM_SCGC5_TSI_SHIFT)20027 #define SIM_WR_SCGC5_TSI(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_TSI_MASK, SIM_SCGC5_TSI(value)…
6338 #define SIM_SCGC5_TSI_MASK (0x20U) macro6340 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
22242 #define SIM_SCGC5_TSI_MASK (0x20U) macro22248 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
23222 #define SIM_SCGC5_TSI_MASK (0x20U) macro23228 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
22356 #define SIM_SCGC5_TSI_MASK (0x20U) macro22362 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
