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Searched refs:SIM_SCGC5_PORTC_MASK (Results 1 – 19 of 19) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dsystem_MKW22D5.c87 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; /* Ungate PORTB and PORTC clock*/ in ExtClk_Setup_HookUp()
DMKW22D5.h6602 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
6604 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dsystem_MKW24D5.c87 SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; /* Ungate PORTB and PORTC clock*/ in ExtClk_Setup_HookUp()
DMKW24D5.h6602 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
6604 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h3817 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
3819 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h12145 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
12151 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h6418 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
6420 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h21799 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
21805 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h6983 #define SIM_SCGC5_PORTC_MASK 0x800u macro
6986 …) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
DMKW40Z4_extension.h20080 #define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_S…
20084 #define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h6347 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
6349 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h6418 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
6420 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h6983 #define SIM_SCGC5_PORTC_MASK 0x800u macro
6986 …) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h6983 #define SIM_SCGC5_PORTC_MASK 0x800u macro
6986 …) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_PORTC_SHIFT))&SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h19772 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
19778 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h22263 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
22269 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h21112 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
21118 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h23243 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
23249 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h22377 #define SIM_SCGC5_PORTC_MASK (0x800U) macro
22383 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)