Searched refs:SIM_SCGC5_LPTMR_MASK (Results 1 – 17 of 17) sorted by relevance
3805 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro3807 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
12124 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro12130 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
6593 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro6595 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
6406 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro6408 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
21775 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro21781 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
6967 #define SIM_SCGC5_LPTMR_MASK 0x1u macro6970 …) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC5_LPTMR_SHIFT))&SIM_SCGC5_LPTMR_MASK)
20004 #define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_S…20008 #define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(…
6335 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro6337 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
19751 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro19757 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
22228 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro22234 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
21091 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro21097 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
23208 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro23214 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
22349 #define SIM_SCGC5_LPTMR_MASK (0x1U) macro22355 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
