Searched refs:SIM_SCGC4_I2C0_MASK (Results 1 – 17 of 17) sorted by relevance
3776 #define SIM_SCGC4_I2C0_MASK (0x40U) macro3778 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
12064 #define SIM_SCGC4_I2C0_MASK (0x40U) macro12070 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
6564 #define SIM_SCGC4_I2C0_MASK (0x40U) macro6566 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
6392 #define SIM_SCGC4_I2C0_MASK (0x40U) macro6394 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
21699 #define SIM_SCGC4_I2C0_MASK (0x40U) macro21705 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
6954 #define SIM_SCGC4_I2C0_MASK 0x40u macro6957 …x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_I2C0_SHIFT))&SIM_SCGC4_I2C0_MASK)
19922 #define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIF…19926 #define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(val…
6321 #define SIM_SCGC4_I2C0_MASK (0x40U) macro6323 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
19674 #define SIM_SCGC4_I2C0_MASK (0x40U) macro19680 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
22189 #define SIM_SCGC4_I2C0_MASK (0x40U) macro22195 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
21014 #define SIM_SCGC4_I2C0_MASK (0x40U) macro21020 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
23169 #define SIM_SCGC4_I2C0_MASK (0x40U) macro23175 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
22282 #define SIM_SCGC4_I2C0_MASK (0x40U) macro22288 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
