Searched refs:SIM_SCGC4_CMP_MASK (Results 1 – 17 of 17) sorted by relevance
3794 #define SIM_SCGC4_CMP_MASK (0x80000U) macro3796 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
12106 #define SIM_SCGC4_CMP_MASK (0x80000U) macro12112 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
6585 #define SIM_SCGC4_CMP_MASK (0x80000U) macro6587 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
6398 #define SIM_SCGC4_CMP_MASK (0x80000U) macro6400 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
21755 #define SIM_SCGC4_CMP_MASK (0x80000U) macro21761 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
6962 #define SIM_SCGC4_CMP_MASK 0x80000u macro6965 …(x) (((uint32_t)(((uint32_t)(x))<<SIM_SCGC4_CMP_SHIFT))&SIM_SCGC4_CMP_MASK)
19960 #define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)19964 #define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)…
6327 #define SIM_SCGC4_CMP_MASK (0x80000U) macro6329 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
19712 #define SIM_SCGC4_CMP_MASK (0x80000U) macro19718 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
22210 #define SIM_SCGC4_CMP_MASK (0x80000U) macro22216 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
21052 #define SIM_SCGC4_CMP_MASK (0x80000U) macro21058 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
23190 #define SIM_SCGC4_CMP_MASK (0x80000U) macro23196 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
22331 #define SIM_SCGC4_CMP_MASK (0x80000U) macro22337 … (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
