1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_QSPI_H_
10 #define _FSL_QSPI_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup qspi_driver
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief QSPI driver version 2.2.1. */
26 #define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
27 /*@}*/
28
29 /*! @brief Macro functions for LUT table */
30 #define QSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
31 (QuadSPI_LUT_INSTR0(cmd0) | QuadSPI_LUT_PAD0(pad0) | QuadSPI_LUT_OPRND0(op0) | QuadSPI_LUT_INSTR1(cmd1) | \
32 QuadSPI_LUT_PAD1(pad1) | QuadSPI_LUT_OPRND1(op1))
33
34 /*! @brief Macro for QSPI LUT command */
35 #define QSPI_CMD (0x1U)
36 #define QSPI_ADDR (0x2U)
37 #define QSPI_DUMMY (0x3U)
38 #define QSPI_MODE (0x4U)
39 #define QSPI_MODE2 (0x5U)
40 #define QSPI_MODE4 (0x6U)
41 #define QSPI_READ (0x7U)
42 #define QSPI_WRITE (0x8U)
43 #define QSPI_JMP_ON_CS (0x9U)
44 #define QSPI_ADDR_DDR (0xAU)
45 #define QSPI_MODE_DDR (0xBU)
46 #define QSPI_MODE2_DDR (0xCU)
47 #define QSPI_MODE4_DDR (0xDU)
48 #define QSPI_READ_DDR (0xEU)
49 #define QSPI_WRITE_DDR (0xFU)
50 #define QSPI_DATA_LEARN (0x10U)
51 #define QSPI_CMD_DDR (0x11U)
52 #define QSPI_CADDR (0x12U)
53 #define QSPI_CADDR_DDR (0x13U)
54 #define QSPI_STOP (0x0U)
55
56 /*! @brief Macro for QSPI PAD */
57 #define QSPI_PAD_1 (0x0U)
58 #define QSPI_PAD_2 (0x1U)
59 #define QSPI_PAD_4 (0x2U)
60 #define QSPI_PAD_8 (0x3U)
61
62 /*! @brief Status structure of QSPI.*/
63 enum
64 {
65 kStatus_QSPI_Idle = MAKE_STATUS(kStatusGroup_QSPI, 0), /*!< QSPI is in idle state */
66 kStatus_QSPI_Busy = MAKE_STATUS(kStatusGroup_QSPI, 1), /*!< QSPI is busy */
67 kStatus_QSPI_Error = MAKE_STATUS(kStatusGroup_QSPI, 2), /*!< Error occurred during QSPI transfer */
68 };
69
70 /*! @brief QSPI read data area, from IP FIFO or AHB buffer.*/
71 typedef enum _qspi_read_area
72 {
73 kQSPI_ReadAHB = 0x0U, /*!< QSPI read from AHB buffer. */
74 kQSPI_ReadIP /*!< QSPI read from IP FIFO. */
75 } qspi_read_area_t;
76
77 /*! @brief QSPI command sequence type */
78 typedef enum _qspi_command_seq
79 {
80 kQSPI_IPSeq = QuadSPI_SPTRCLR_IPPTRC_MASK, /*!< IP command sequence */
81 kQSPI_BufferSeq = QuadSPI_SPTRCLR_BFPTRC_MASK, /*!< Buffer command sequence */
82 kQSPI_AllSeq = QuadSPI_SPTRCLR_IPPTRC_MASK | QuadSPI_SPTRCLR_BFPTRC_MASK /* All command sequence */
83 } qspi_command_seq_t;
84
85 /*! @brief QSPI buffer type */
86 typedef enum _qspi_fifo
87 {
88 kQSPI_TxFifo = QuadSPI_MCR_CLR_TXF_MASK, /*!< QSPI Tx FIFO */
89 kQSPI_RxFifo = QuadSPI_MCR_CLR_RXF_MASK, /*!< QSPI Rx FIFO */
90 kQSPI_AllFifo = QuadSPI_MCR_CLR_TXF_MASK | QuadSPI_MCR_CLR_RXF_MASK /*!< QSPI all FIFO, including Tx and Rx */
91 } qspi_fifo_t;
92
93 /*! @brief QSPI transfer endianess*/
94 typedef enum _qspi_endianness
95 {
96 kQSPI_64BigEndian = 0x0U, /*!< 64 bits big endian */
97 kQSPI_32LittleEndian, /*!< 32 bit little endian */
98 kQSPI_32BigEndian, /*!< 32 bit big endian */
99 kQSPI_64LittleEndian /*!< 64 bit little endian */
100 } qspi_endianness_t;
101
102 /*! @brief QSPI error flags */
103 enum _qspi_error_flags
104 {
105 kQSPI_DataLearningFail = (int)QuadSPI_FR_DLPFF_MASK, /*!< Data learning pattern failure flag */
106 kQSPI_TxBufferFill = QuadSPI_FR_TBFF_MASK, /*!< Tx buffer fill flag */
107 kQSPI_TxBufferUnderrun = QuadSPI_FR_TBUF_MASK, /*!< Tx buffer underrun flag */
108 kQSPI_IllegalInstruction = QuadSPI_FR_ILLINE_MASK, /*!< Illegal instruction error flag */
109 kQSPI_RxBufferOverflow = QuadSPI_FR_RBOF_MASK, /*!< Rx buffer overflow flag */
110 kQSPI_RxBufferDrain = QuadSPI_FR_RBDF_MASK, /*!< Rx buffer drain flag */
111 kQSPI_AHBSequenceError = QuadSPI_FR_ABSEF_MASK, /*!< AHB sequence error flag */
112 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
113 kQSPI_AHBIllegalTransaction = QuadSPI_FR_AITEF_MASK, /*!< AHB illegal transaction error flag */
114 #endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
115 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
116 kQSPI_AHBIllegalBurstSize = QuadSPI_FR_AIBSEF_MASK, /*!< AHB illegal burst error flag */
117 #endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
118 kQSPI_AHBBufferOverflow = QuadSPI_FR_ABOF_MASK, /*!< AHB buffer overflow flag */
119 #if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
120 kQSPI_IPCommandUsageError = QuadSPI_FR_IUEF_MASK, /*!< IP command usage error flag */
121 #endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
122 kQSPI_IPCommandTriggerDuringAHBAccess = QuadSPI_FR_IPAEF_MASK, /*!< IP command trigger during AHB access error */
123 kQSPI_IPCommandTriggerDuringIPAccess = QuadSPI_FR_IPIEF_MASK, /*!< IP command trigger cannot be executed */
124 kQSPI_IPCommandTriggerDuringAHBGrant = QuadSPI_FR_IPGEF_MASK, /*!< IP command trigger during AHB grant error */
125 kQSPI_IPCommandTransactionFinished = QuadSPI_FR_TFF_MASK, /*!< IP command transaction finished flag */
126 kQSPI_FlagAll = (int)0x8C83F8D1U /*!< All error flag */
127 };
128
129 /*! @brief QSPI state bit */
130 enum _qspi_flags
131 {
132 kQSPI_DataLearningSamplePoint = (int)QuadSPI_SR_DLPSMP_MASK, /*!< Data learning sample point */
133 kQSPI_TxBufferFull = QuadSPI_SR_TXFULL_MASK, /*!< Tx buffer full flag */
134 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
135 kQSPI_TxDMA = QuadSPI_SR_TXDMA_MASK, /*!< Tx DMA is requested or running */
136 kQSPI_TxWatermark = QuadSPI_SR_TXWA_MASK, /*!< Tx buffer watermark available */
137 #endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
138 kQSPI_TxBufferEnoughData = QuadSPI_SR_TXEDA_MASK, /*!< Tx buffer enough data available */
139 kQSPI_RxDMA = QuadSPI_SR_RXDMA_MASK, /*!< Rx DMA is requesting or running */
140 kQSPI_RxBufferFull = QuadSPI_SR_RXFULL_MASK, /*!< Rx buffer full */
141 kQSPI_RxWatermark = QuadSPI_SR_RXWE_MASK, /*!< Rx buffer watermark exceeded */
142 kQSPI_AHB3BufferFull = QuadSPI_SR_AHB3FUL_MASK, /*!< AHB buffer 3 full*/
143 kQSPI_AHB2BufferFull = QuadSPI_SR_AHB2FUL_MASK, /*!< AHB buffer 2 full */
144 kQSPI_AHB1BufferFull = QuadSPI_SR_AHB1FUL_MASK, /*!< AHB buffer 1 full */
145 kQSPI_AHB0BufferFull = QuadSPI_SR_AHB0FUL_MASK, /*!< AHB buffer 0 full */
146 kQSPI_AHB3BufferNotEmpty = QuadSPI_SR_AHB3NE_MASK, /*!< AHB buffer 3 not empty */
147 kQSPI_AHB2BufferNotEmpty = QuadSPI_SR_AHB2NE_MASK, /*!< AHB buffer 2 not empty */
148 kQSPI_AHB1BufferNotEmpty = QuadSPI_SR_AHB1NE_MASK, /*!< AHB buffer 1 not empty */
149 kQSPI_AHB0BufferNotEmpty = QuadSPI_SR_AHB0NE_MASK, /*!< AHB buffer 0 not empty */
150 kQSPI_AHBTransactionPending = QuadSPI_SR_AHBTRN_MASK, /*!< AHB access transaction pending */
151 kQSPI_AHBCommandPriorityGranted = QuadSPI_SR_AHBGNT_MASK, /*!< AHB command priority granted */
152 kQSPI_AHBAccess = QuadSPI_SR_AHB_ACC_MASK, /*!< AHB access */
153 kQSPI_IPAccess = QuadSPI_SR_IP_ACC_MASK, /*!< IP access */
154 kQSPI_Busy = QuadSPI_SR_BUSY_MASK, /*!< Module busy */
155 kQSPI_StateAll = (int)0xEF897FE7U /*!< All flags */
156 };
157
158 /*! @brief QSPI interrupt enable */
159 enum _qspi_interrupt_enable
160 {
161 kQSPI_DataLearningFailInterruptEnable =
162 (int)QuadSPI_RSER_DLPFIE_MASK, /*!< Data learning pattern failure interrupt enable */
163 kQSPI_TxBufferFillInterruptEnable = QuadSPI_RSER_TBFIE_MASK, /*!< Tx buffer fill interrupt enable */
164 kQSPI_TxBufferUnderrunInterruptEnable = QuadSPI_RSER_TBUIE_MASK, /*!< Tx buffer underrun interrupt enable */
165 kQSPI_IllegalInstructionInterruptEnable =
166 QuadSPI_RSER_ILLINIE_MASK, /*!< Illegal instruction error interrupt enable */
167 kQSPI_RxBufferOverflowInterruptEnable = QuadSPI_RSER_RBOIE_MASK, /*!< Rx buffer overflow interrupt enable */
168 kQSPI_RxBufferDrainInterruptEnable = QuadSPI_RSER_RBDIE_MASK, /*!< Rx buffer drain interrupt enable */
169 kQSPI_AHBSequenceErrorInterruptEnable = QuadSPI_RSER_ABSEIE_MASK, /*!< AHB sequence error interrupt enable */
170 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AITEF) || (!FSL_FEATURE_QSPI_HAS_NO_AITEF)
171 kQSPI_AHBIllegalTransactionInterruptEnable =
172 QuadSPI_RSER_AITIE_MASK, /*!< AHB illegal transaction error interrupt enable */
173 #endif /* FSL_FEATURE_QSPI_HAS_NO_AITEF */
174 #if !defined(FSL_FEATURE_QSPI_HAS_NO_AIBSEF) || (!FSL_FEATURE_QSPI_HAS_NO_AIBSEF)
175 kQSPI_AHBIllegalBurstSizeInterruptEnable =
176 QuadSPI_RSER_AIBSIE_MASK, /*!< AHB illegal burst error interrupt enable */
177 #endif /* FSL_FEATURE_QSPI_HAS_NO_AIBSEF */
178 kQSPI_AHBBufferOverflowInterruptEnable = QuadSPI_RSER_ABOIE_MASK, /*!< AHB buffer overflow interrupt enable */
179 #if defined(FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR) && (FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR)
180 kQSPI_IPCommandUsageErrorInterruptEnable = QuadSPI_RSER_IUEIE_MASK, /*!< IP command usage error interrupt enable */
181 #endif /* FSL_FEATURE_QSPI_HAS_IP_COMMAND_USAGE_ERROR */
182 kQSPI_IPCommandTriggerDuringAHBAccessInterruptEnable =
183 QuadSPI_RSER_IPAEIE_MASK, /*!< IP command trigger during AHB access error */
184 kQSPI_IPCommandTriggerDuringIPAccessInterruptEnable =
185 QuadSPI_RSER_IPIEIE_MASK, /*!< IP command trigger cannot be executed */
186 kQSPI_IPCommandTriggerDuringAHBGrantInterruptEnable =
187 QuadSPI_RSER_IPGEIE_MASK, /*!< IP command trigger during AHB grant error */
188 kQSPI_IPCommandTransactionFinishedInterruptEnable =
189 QuadSPI_RSER_TFIE_MASK, /*!< IP command transaction finished interrupt enable */
190 kQSPI_AllInterruptEnable = (int)0x8C83F8D1U /*!< All error interrupt enable */
191 };
192
193 /*! @brief QSPI DMA request flag */
194 enum _qspi_dma_enable
195 {
196 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
197 kQSPI_TxBufferFillDMAEnable = QuadSPI_RSER_TBFDE_MASK, /*!< Tx buffer fill DMA */
198 #endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
199 kQSPI_RxBufferDrainDMAEnable = QuadSPI_RSER_RBDDE_MASK, /*!< Rx buffer drain DMA */
200 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TXDMA) || (!FSL_FEATURE_QSPI_HAS_NO_TXDMA)
201 kQSPI_AllDDMAEnable = QuadSPI_RSER_TBFDE_MASK | QuadSPI_RSER_RBDDE_MASK /*!< All DMA source */
202 #else
203 kQSPI_AllDDMAEnable = QuadSPI_RSER_RBDDE_MASK /* All DMA source */
204 #endif /* FSL_FEATURE_QSPI_HAS_NO_TXDMA */
205 };
206
207 /*! @brief Phrase shift number for DQS mode. */
208 typedef enum _qspi_dqs_phrase_shift
209 {
210 kQSPI_DQSNoPhraseShift = 0x0U, /*!< No phase shift */
211 kQSPI_DQSPhraseShift45Degree, /*!< Select 45 degree phase shift*/
212 kQSPI_DQSPhraseShift90Degree, /*!< Select 90 degree phase shift */
213 kQSPI_DQSPhraseShift135Degree /*!< Select 135 degree phase shift */
214 } qspi_dqs_phrase_shift_t;
215
216 /*! @brief Qspi read sampling option. */
217 typedef enum _qspi_dqs_read_sample_clock
218 {
219 kQSPI_ReadSampleClkInternalLoopback = 0x0U, /*!< Read sample clock adopts internal loopback mode. */
220 kQSPI_ReadSampleClkLoopbackFromDqsPad = 0x1U, /*!< Dummy Read strobe generated by QSPI Controller
221 and loopback from DQS pad. */
222 kQSPI_ReadSampleClkExternalInputFromDqsPad = 0x2U, /*!< Flash provided Read strobe and input from DQS pad. */
223 } qspi_dqs_read_sample_clock_t;
224
225 /*! @brief DQS configure features*/
226 typedef struct QspiDQSConfig
227 {
228 uint32_t portADelayTapNum; /*!< Delay chain tap number selection for QSPI port A DQS */
229 #if defined(QuadSPI_SOCCR_DQS_IFB_DELAY_CHAIN_SEL_MASK)
230 uint32_t portBDelayTapNum; /*!< Delay chain tap number selection for QSPI port B DQS*/
231 #endif
232 qspi_dqs_phrase_shift_t shift; /*!< Phase shift for internal DQS generation */
233 qspi_dqs_read_sample_clock_t rxSampleClock; /*!< Read sample clock for Dqs. */
234 bool enableDQSClkInverse; /*!< Enable inverse clock for internal DQS generation */
235 } qspi_dqs_config_t;
236
237 /*! @brief Flash timing configuration. */
238 typedef struct QspiFlashTiming
239 {
240 uint32_t dataHoldTime; /*!< Serial flash data in hold time */
241 uint32_t CSHoldTime; /*!< Serial flash CS hold time in terms of serial flash clock cycles */
242 uint32_t CSSetupTime; /*!< Serial flash CS setup time in terms of serial flash clock cycles */
243 } qspi_flash_timing_t;
244
245 /*! @brief QSPI configuration structure*/
246 typedef struct QspiConfig
247 {
248 uint32_t clockSource; /*!< Clock source for QSPI module */
249 uint32_t baudRate; /*!< Serial flash clock baud rate */
250 uint8_t txWatermark; /*!< QSPI transmit watermark value */
251 uint8_t rxWatermark; /*!< QSPI receive watermark value. */
252 uint32_t AHBbufferSize[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
253 uint8_t AHBbufferMaster[FSL_FEATURE_QSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer master. */
254 bool enableAHBbuffer3AllMaster; /*!< Is AHB buffer3 for all master.*/
255 qspi_read_area_t area; /*!< Which area Rx data readout */
256 bool enableQspi; /*!< Enable QSPI after initialization */
257 } qspi_config_t;
258
259 /*! @brief External flash configuration items*/
260 typedef struct _qspi_flash_config
261 {
262 uint32_t flashA1Size; /*!< Flash A1 size */
263 uint32_t flashA2Size; /*!< Flash A2 size */
264 #if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
265 uint32_t flashB1Size; /*!< Flash B1 size */
266 uint32_t flashB2Size; /*!< Flash B2 size */
267 #endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
268 uint32_t lookuptable[FSL_FEATURE_QSPI_LUT_DEPTH]; /*!< Flash command in LUT */
269 #if !defined(FSL_FEATURE_QSPI_HAS_NO_TDH) || (!FSL_FEATURE_QSPI_HAS_NO_TDH)
270 uint32_t dataHoldTime; /*!< Data line hold time. */
271 #endif /* FSL_FEATURE_QSPI_HAS_NO_TDH */
272 uint32_t CSHoldTime; /*!< CS line hold time */
273 uint32_t CSSetupTime; /*!< CS line setup time*/
274 uint32_t cloumnspace; /*!< Column space size */
275 uint32_t dataLearnValue; /*!< Data Learn value if enable data learn */
276 qspi_endianness_t endian; /*!< Flash data endianess. */
277 bool enableWordAddress; /*!< If enable word address.*/
278 } qspi_flash_config_t;
279
280 /*! @brief Transfer structure for QSPI */
281 typedef struct _qspi_transfer
282 {
283 uint32_t *data; /*!< Pointer to data to transmit */
284 size_t dataSize; /*!< Bytes to be transmit */
285 } qspi_transfer_t;
286
287 /*! @brief 16-bit access reg for IPCR register */
288 typedef struct _ip_command_config
289 {
290 union
291 {
292 __IO uint32_t IPCR; /*!< IP Configuration Register */
293 struct
294 {
295 __IO uint16_t IDATZ; /*!< 16-bit access for IDATZ field in IPCR register */
296 __IO uint8_t RESERVED_0; /*!< 8-bit access for RESERVED_0 field in IPCR register */
297 __IO uint8_t SEQID; /*!< 8-bit access for SEQID field in IPCR register */
298 } BITFIELD;
299 } IPCR_REG;
300 } ip_command_config_t;
301
302 /******************************************************************************
303 * API
304 *****************************************************************************/
305 #if defined(__cplusplus)
306 extern "C" {
307 #endif
308
309 /*!
310 * @name Initialization and deinitialization
311 * @{
312 */
313
314 /*!
315 * @brief Get the instance number for QSPI.
316 *
317 * @param base QSPI base pointer.
318 */
319 uint32_t QSPI_GetInstance(QuadSPI_Type *base);
320
321 /*!
322 * @brief Initializes the QSPI module and internal state.
323 *
324 * This function enables the clock for QSPI and also configures the QSPI with the
325 * input configure parameters. Users should call this function before any QSPI operations.
326 *
327 * @param base Pointer to QuadSPI Type.
328 * @param config QSPI configure structure.
329 * @param srcClock_Hz QSPI source clock frequency in Hz.
330 */
331 void QSPI_Init(QuadSPI_Type *base, qspi_config_t *config, uint32_t srcClock_Hz);
332
333 /*!
334 * @brief Gets default settings for QSPI.
335 *
336 * @param config QSPI configuration structure.
337 */
338 void QSPI_GetDefaultQspiConfig(qspi_config_t *config);
339
340 /*!
341 * @brief Deinitializes the QSPI module.
342 *
343 * Clears the QSPI state and QSPI module registers.
344 * @param base Pointer to QuadSPI Type.
345 */
346 void QSPI_Deinit(QuadSPI_Type *base);
347
348 /*!
349 * @brief Configures the serial flash parameter.
350 *
351 * This function configures the serial flash relevant parameters, such as the size, command, and so on.
352 * The flash configuration value cannot have a default value. The user needs to configure it according to the
353 * QSPI features.
354 *
355 * @param base Pointer to QuadSPI Type.
356 * @param config Flash configuration parameters.
357 */
358 void QSPI_SetFlashConfig(QuadSPI_Type *base, qspi_flash_config_t *config);
359
360 #if (!defined(FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG)) || !FSL_FEATURE_QSPI_HAS_NO_SOCCR_REG
361 /*!
362 * @brief Configures the serial flash DQS parameter.
363 *
364 * This function configures the serial flash DQS relevant parameters, such as the delay chain tap number, .
365 * DQS shift phase, whether need to inverse and the rxc sample clock selection.
366 *
367 * @param base Pointer to QuadSPI Type.
368 * @param config Dqs configuration parameters.
369 */
370 void QSPI_SetDqsConfig(QuadSPI_Type *base, qspi_dqs_config_t *config);
371 #endif
372
373 /*!
374 * @brief Software reset for the QSPI logic.
375 *
376 * This function sets the software reset flags for both AHB and buffer domain and
377 * resets both AHB buffer and also IP FIFOs.
378 *
379 * @param base Pointer to QuadSPI Type.
380 */
381 void QSPI_SoftwareReset(QuadSPI_Type *base);
382
383 /*!
384 * @brief Enables or disables the QSPI module.
385 *
386 * @param base Pointer to QuadSPI Type.
387 * @param enable True means enable QSPI, false means disable.
388 */
QSPI_Enable(QuadSPI_Type * base,bool enable)389 static inline void QSPI_Enable(QuadSPI_Type *base, bool enable)
390 {
391 if (enable)
392 {
393 base->MCR &= ~QuadSPI_MCR_MDIS_MASK;
394 }
395 else
396 {
397 base->MCR |= QuadSPI_MCR_MDIS_MASK;
398 }
399 }
400
401 /*! @} */
402
403 /*!
404 * @name Status
405 * @{
406 */
407
408 /*!
409 * @brief Gets the state value of QSPI.
410 *
411 * @param base Pointer to QuadSPI Type.
412 * @return status flag, use status flag to AND #_qspi_flags could get the related status.
413 */
QSPI_GetStatusFlags(QuadSPI_Type * base)414 static inline uint32_t QSPI_GetStatusFlags(QuadSPI_Type *base)
415 {
416 return base->SR;
417 }
418
419 /*!
420 * @brief Gets QSPI error status flags.
421 *
422 * @param base Pointer to QuadSPI Type.
423 * @return status flag, use status flag to AND #_qspi_error_flags could get the related status.
424 */
QSPI_GetErrorStatusFlags(QuadSPI_Type * base)425 static inline uint32_t QSPI_GetErrorStatusFlags(QuadSPI_Type *base)
426 {
427 return base->FR;
428 }
429
430 /*! @brief Clears the QSPI error flags.
431 *
432 * @param base Pointer to QuadSPI Type.
433 * @param mask Which kind of QSPI flags to be cleared, a combination of _qspi_error_flags.
434 */
QSPI_ClearErrorFlag(QuadSPI_Type * base,uint32_t mask)435 static inline void QSPI_ClearErrorFlag(QuadSPI_Type *base, uint32_t mask)
436 {
437 base->FR = mask;
438 }
439
440 /*! @} */
441
442 /*!
443 * @name Interrupts
444 * @{
445 */
446
447 /*!
448 * @brief Enables the QSPI interrupts.
449 *
450 * @param base Pointer to QuadSPI Type.
451 * @param mask QSPI interrupt source.
452 */
QSPI_EnableInterrupts(QuadSPI_Type * base,uint32_t mask)453 static inline void QSPI_EnableInterrupts(QuadSPI_Type *base, uint32_t mask)
454 {
455 base->RSER |= mask;
456 }
457
458 /*!
459 * @brief Disables the QSPI interrupts.
460 *
461 * @param base Pointer to QuadSPI Type.
462 * @param mask QSPI interrupt source.
463 */
QSPI_DisableInterrupts(QuadSPI_Type * base,uint32_t mask)464 static inline void QSPI_DisableInterrupts(QuadSPI_Type *base, uint32_t mask)
465 {
466 base->RSER &= ~mask;
467 }
468
469 /*! @} */
470
471 /*!
472 * @name DMA Control
473 * @{
474 */
475
476 /*!
477 * @brief Enables the QSPI DMA source.
478 *
479 * @param base Pointer to QuadSPI Type.
480 * @param mask QSPI DMA source.
481 * @param enable True means enable DMA, false means disable.
482 */
QSPI_EnableDMA(QuadSPI_Type * base,uint32_t mask,bool enable)483 static inline void QSPI_EnableDMA(QuadSPI_Type *base, uint32_t mask, bool enable)
484 {
485 if (enable)
486 {
487 base->RSER |= mask;
488 }
489 else
490 {
491 base->RSER &= ~mask;
492 }
493 }
494
495 /*!
496 * @brief Gets the Tx data register address. It is used for DMA operation.
497 *
498 * @param base Pointer to QuadSPI Type.
499 * @return QSPI Tx data register address.
500 */
QSPI_GetTxDataRegisterAddress(QuadSPI_Type * base)501 static inline uint32_t QSPI_GetTxDataRegisterAddress(QuadSPI_Type *base)
502 {
503 return (uint32_t)(&base->TBDR);
504 }
505
506 /*!
507 * @brief Gets the Rx data register address used for DMA operation.
508 *
509 * This function returns the Rx data register address or Rx buffer address
510 * according to the Rx read area settings.
511 *
512 * @param base Pointer to QuadSPI Type.
513 * @return QSPI Rx data register address.
514 */
515 uint32_t QSPI_GetRxDataRegisterAddress(QuadSPI_Type *base);
516
517 /* @} */
518
519 /*!
520 * @name Bus Operations
521 * @{
522 */
523
524 /*! @brief Sets the IP command address.
525 *
526 * @param base Pointer to QuadSPI Type.
527 * @param addr IP command address.
528 */
QSPI_SetIPCommandAddress(QuadSPI_Type * base,uint32_t addr)529 static inline void QSPI_SetIPCommandAddress(QuadSPI_Type *base, uint32_t addr)
530 {
531 base->SFAR = addr;
532 }
533
534 /*! @brief Sets the IP command size.
535 *
536 * @param base Pointer to QuadSPI Type.
537 * @param size IP command size.
538 */
QSPI_SetIPCommandSize(QuadSPI_Type * base,uint32_t size)539 static inline void QSPI_SetIPCommandSize(QuadSPI_Type *base, uint32_t size)
540 {
541 union
542 {
543 volatile uint32_t *commandRegBase;
544 ip_command_config_t *commandConfigPtr;
545 } command;
546 command.commandRegBase = &(base->IPCR);
547 ip_command_config_t *ipCommand = command.commandConfigPtr;
548 size = QuadSPI_IPCR_IDATSZ(size);
549 ipCommand->IPCR_REG.BITFIELD.IDATZ = (uint16_t)size;
550 }
551
552 /*! @brief Executes IP commands located in LUT table.
553 *
554 * @param base Pointer to QuadSPI Type.
555 * @param index IP command located in which LUT table index.
556 */
557 void QSPI_ExecuteIPCommand(QuadSPI_Type *base, uint32_t index);
558
559 /*! @brief Executes AHB commands located in LUT table.
560 *
561 * @param base Pointer to QuadSPI Type.
562 * @param index AHB command located in which LUT table index.
563 */
564 void QSPI_ExecuteAHBCommand(QuadSPI_Type *base, uint32_t index);
565
566 #if defined(FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE) && (FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE)
567 /*! @brief Enables/disables the QSPI IP command parallel mode.
568 *
569 * @param base Pointer to QuadSPI Type.
570 * @param enable True means enable parallel mode, false means disable parallel mode.
571 */
QSPI_EnableIPParallelMode(QuadSPI_Type * base,bool enable)572 static inline void QSPI_EnableIPParallelMode(QuadSPI_Type *base, bool enable)
573 {
574 if (enable)
575 {
576 base->IPCR |= QuadSPI_IPCR_PAR_EN_MASK;
577 }
578 else
579 {
580 base->IPCR &= ~QuadSPI_IPCR_PAR_EN_MASK;
581 }
582 }
583
584 /*! @brief Enables/disables the QSPI AHB command parallel mode.
585 *
586 * @param base Pointer to QuadSPI Type.
587 * @param enable True means enable parallel mode, false means disable parallel mode.
588 */
QSPI_EnableAHBParallelMode(QuadSPI_Type * base,bool enable)589 static inline void QSPI_EnableAHBParallelMode(QuadSPI_Type *base, bool enable)
590 {
591 if (enable)
592 {
593 base->BFGENCR |= QuadSPI_BFGENCR_PAR_EN_MASK;
594 }
595 else
596 {
597 base->BFGENCR &= ~QuadSPI_BFGENCR_PAR_EN_MASK;
598 }
599 }
600 #endif /* FSL_FEATURE_QSPI_SUPPORT_PARALLEL_MODE */
601
602 /*! @brief Updates the LUT table.
603 *
604 * @param base Pointer to QuadSPI Type.
605 * @param index Which LUT index needs to be located. It should be an integer divided by 4.
606 * @param cmd Command sequence array.
607 */
608 void QSPI_UpdateLUT(QuadSPI_Type *base, uint32_t index, uint32_t *cmd);
609
610 /*! @brief Clears the QSPI FIFO logic.
611 *
612 * @param base Pointer to QuadSPI Type.
613 * @param mask Which kind of QSPI FIFO to be cleared.
614 */
QSPI_ClearFifo(QuadSPI_Type * base,uint32_t mask)615 static inline void QSPI_ClearFifo(QuadSPI_Type *base, uint32_t mask)
616 {
617 base->MCR |= mask;
618 }
619
620 /*!@ brief Clears the command sequence for the IP/buffer command.
621 *
622 * This function can reset the command sequence.
623 * @param base QSPI base address.
624 * @param seq Which command sequence need to reset, IP command, buffer command or both.
625 */
QSPI_ClearCommandSequence(QuadSPI_Type * base,qspi_command_seq_t seq)626 static inline void QSPI_ClearCommandSequence(QuadSPI_Type *base, qspi_command_seq_t seq)
627 {
628 base->SPTRCLR = (uint32_t)seq;
629 }
630
631 /*!
632 * @brief Enable or disable DDR mode.
633 *
634 * @param base QSPI base pointer
635 * @param enable True means enable DDR mode, false means disable DDR mode.
636 */
QSPI_EnableDDRMode(QuadSPI_Type * base,bool enable)637 static inline void QSPI_EnableDDRMode(QuadSPI_Type *base, bool enable)
638 {
639 if (enable)
640 {
641 base->MCR |= QuadSPI_MCR_DDR_EN_MASK;
642 }
643 else
644 {
645 base->MCR &= ~QuadSPI_MCR_DDR_EN_MASK;
646 }
647 }
648
649 #if defined(FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC) && (FSL_FEATURE_QSPI_SOCCR_HAS_CLR_LPCAC)
650
651 /*! @brief Clears the QSPI cache.
652 *
653 * @param base Pointer to QuadSPI Type.
654 */
655 void QSPI_ClearCache(QuadSPI_Type *base);
656 #endif
657
658 /*!@ brief Set the RX buffer readout area.
659 *
660 * This function can set the RX buffer readout, from AHB bus or IP Bus.
661 * @param base QSPI base address.
662 * @param area QSPI Rx buffer readout area. AHB bus buffer or IP bus buffer.
663 */
664 void QSPI_SetReadDataArea(QuadSPI_Type *base, qspi_read_area_t area);
665
666 /*!
667 * @brief Sends a buffer of data bytes using a blocking method.
668 * @note This function blocks via polling until all bytes have been sent.
669 * @param base QSPI base pointer
670 * @param buffer The data bytes to send
671 * @param size The number of data bytes to send
672 */
673 void QSPI_WriteBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
674
675 /*!
676 * @brief Writes data into FIFO.
677 *
678 * @param base QSPI base pointer
679 * @param data The data bytes to send
680 */
QSPI_WriteData(QuadSPI_Type * base,uint32_t data)681 static inline void QSPI_WriteData(QuadSPI_Type *base, uint32_t data)
682 {
683 base->TBDR = data;
684 }
685
686 /*!
687 * @brief Receives a buffer of data bytes using a blocking method.
688 * @note This function blocks via polling until all bytes have been sent. Users shall notice that
689 * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
690 * For flash contents read, please use AHB bus read, this is much more efficiency.
691 *
692 * @param base QSPI base pointer
693 * @param buffer The data bytes to send
694 * @param size The number of data bytes to receive
695 */
696 void QSPI_ReadBlocking(QuadSPI_Type *base, uint32_t *buffer, size_t size);
697
698 /*!
699 * @brief Receives data from data FIFO.
700 *
701 * @param base QSPI base pointer
702 * @return The data in the FIFO.
703 */
704 uint32_t QSPI_ReadData(QuadSPI_Type *base);
705
706 /*! @} */
707
708 /*!
709 * @name Transactional
710 * @{
711 */
712
713 /*!
714 * @brief Writes data to the QSPI transmit buffer.
715 *
716 * This function writes a continuous data to the QSPI transmit FIFO. This function is a block function
717 * and can return only when finished. This function uses polling methods.
718 *
719 * @param base Pointer to QuadSPI Type.
720 * @param xfer QSPI transfer structure.
721 */
QSPI_TransferSendBlocking(QuadSPI_Type * base,qspi_transfer_t * xfer)722 static inline void QSPI_TransferSendBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
723 {
724 QSPI_WriteBlocking(base, xfer->data, xfer->dataSize);
725 }
726
727 /*!
728 * @brief Reads data from the QSPI receive buffer in polling way.
729 *
730 * This function reads continuous data from the QSPI receive buffer/FIFO. This function is a blocking
731 * function and can return only when finished. This function uses polling methods. Users shall notice that
732 * this receive size shall not bigger than 64 bytes. As this interface is used to read flash status registers.
733 * For flash contents read, please use AHB bus read, this is much more efficiency.
734 *
735 * @param base Pointer to QuadSPI Type.
736 * @param xfer QSPI transfer structure.
737 */
QSPI_TransferReceiveBlocking(QuadSPI_Type * base,qspi_transfer_t * xfer)738 static inline void QSPI_TransferReceiveBlocking(QuadSPI_Type *base, qspi_transfer_t *xfer)
739 {
740 QSPI_ReadBlocking(base, xfer->data, xfer->dataSize);
741 }
742
743 /*! @} */
744
745 #if defined(__cplusplus)
746 }
747 #endif
748
749 /* @}*/
750
751 #endif /* _FSL_QSPI_H_*/
752
