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Searched refs:PIT_TCTRL_TEN_MASK (Results 1 – 25 of 32) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_pit.h290 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; in PIT_StartTimer()
304 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; in PIT_StopTimer()
Dfsl_pit.c86 base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK); in PIT_Init()
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_pit.h290 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_TEN_MASK; in PIT_StartTimer()
304 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_TEN_MASK; in PIT_StopTimer()
Dfsl_pit.c86 base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK); in PIT_Init()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h2974 #define PIT_TCTRL_TEN_MASK (0x1U) macro
2976 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h9950 #define PIT_TCTRL_TEN_MASK (0x1U) macro
9956 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h5495 #define PIT_TCTRL_TEN_MASK (0x1U) macro
5497 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h5495 #define PIT_TCTRL_TEN_MASK (0x1U) macro
5497 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h5187 #define PIT_TCTRL_TEN_MASK (0x1U) macro
5189 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h18098 #define PIT_TCTRL_TEN_MASK (0x1U) macro
18104 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h5506 #define PIT_TCTRL_TEN_MASK 0x1u macro
5509 …(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h5116 #define PIT_TCTRL_TEN_MASK (0x1U) macro
5118 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h5187 #define PIT_TCTRL_TEN_MASK (0x1U) macro
5189 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h5506 #define PIT_TCTRL_TEN_MASK 0x1u macro
5509 …(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h5506 #define PIT_TCTRL_TEN_MASK 0x1u macro
5509 …(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_TEN_SHIFT))&PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h16551 #define PIT_TCTRL_TEN_MASK (0x1U) macro
16557 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h17762 #define PIT_TCTRL_TEN_MASK (0x1U) macro
17768 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h17891 #define PIT_TCTRL_TEN_MASK (0x1U) macro
17897 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h18735 #define PIT_TCTRL_TEN_MASK (0x1U) macro
18741 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h18423 #define PIT_TCTRL_TEN_MASK (0x1U) macro
18429 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h19366 #define PIT_TCTRL_TEN_MASK (0x1U) macro
19372 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h21727 #define PIT_TCTRL_TEN_MASK (0x1U) macro
21733 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h29047 #define PIT_TCTRL_TEN_MASK (0x1U) macro
29053 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h29029 #define PIT_TCTRL_TEN_MASK (0x1U) macro
29035 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h26338 #define PIT_TCTRL_TEN_MASK (0x1U) macro
26344 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)

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