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Searched refs:PIT_TCTRL_CHN_MASK (Results 1 – 25 of 32) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_pit.h134 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
138 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
Dfsl_pit.c86 base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK); in PIT_Init()
/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_pit.h134 base->CHANNEL[channel].TCTRL |= PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
138 base->CHANNEL[channel].TCTRL &= ~PIT_TCTRL_CHN_MASK; in PIT_SetTimerChainMode()
Dfsl_pit.c86 base->CHANNEL[i].TCTRL &= ~(PIT_TCTRL_TEN_MASK | PIT_TCTRL_TIE_MASK | PIT_TCTRL_CHN_MASK); in PIT_Init()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h2980 #define PIT_TCTRL_CHN_MASK (0x4U) macro
2982 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h9964 #define PIT_TCTRL_CHN_MASK (0x4U) macro
9970 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h5501 #define PIT_TCTRL_CHN_MASK (0x4U) macro
5503 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h5501 #define PIT_TCTRL_CHN_MASK (0x4U) macro
5503 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h5193 #define PIT_TCTRL_CHN_MASK (0x4U) macro
5195 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h18114 #define PIT_TCTRL_CHN_MASK (0x4U) macro
18120 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h5514 #define PIT_TCTRL_CHN_MASK 0x4u macro
5517 …(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h5122 #define PIT_TCTRL_CHN_MASK (0x4U) macro
5124 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h5193 #define PIT_TCTRL_CHN_MASK (0x4U) macro
5195 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h5514 #define PIT_TCTRL_CHN_MASK 0x4u macro
5517 …(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h5514 #define PIT_TCTRL_CHN_MASK 0x4u macro
5517 …(x) (((uint32_t)(((uint32_t)(x))<<PIT_TCTRL_CHN_SHIFT))&PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h16565 #define PIT_TCTRL_CHN_MASK (0x4U) macro
16571 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h17776 #define PIT_TCTRL_CHN_MASK (0x4U) macro
17782 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h17905 #define PIT_TCTRL_CHN_MASK (0x4U) macro
17911 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h18749 #define PIT_TCTRL_CHN_MASK (0x4U) macro
18755 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h18437 #define PIT_TCTRL_CHN_MASK (0x4U) macro
18443 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h19380 #define PIT_TCTRL_CHN_MASK (0x4U) macro
19386 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h21741 #define PIT_TCTRL_CHN_MASK (0x4U) macro
21747 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h29063 #define PIT_TCTRL_CHN_MASK (0x4U) macro
29069 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h29045 #define PIT_TCTRL_CHN_MASK (0x4U) macro
29051 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h26352 #define PIT_TCTRL_CHN_MASK (0x4U) macro
26358 … (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)

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