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Searched refs:PIT_CVAL_TVL_MASK (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h2966 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
2968 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h9940 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
9942 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h5487 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
5489 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h5487 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
5489 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h5179 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
5181 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h18085 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
18089 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h5501 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu macro
5504 …L(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h5108 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
5110 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h5179 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
5181 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h5501 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu macro
5504 …L(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h5501 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu macro
5504 …L(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h16541 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
16543 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h17752 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
17754 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h17881 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
17883 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h18725 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
18727 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h18413 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
18415 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h19354 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
19358 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h21715 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
21719 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h29034 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
29038 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h29016 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
29020 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h26326 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
26330 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h32409 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
32413 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h28566 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
28570 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h34874 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
34878 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h34800 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) macro
34804 … (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)

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