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Searched refs:PDDR (Results 1 – 24 of 24) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_gpio.c104 base->PDDR &= GPIO_FIT_REG(~(1UL << pin)); in GPIO_PinInit()
109 base->PDDR |= GPIO_FIT_REG((1UL << pin)); in GPIO_PinInit()
314 base->PDDR &= ~(1UL << pin); in FGPIO_PinInit()
319 base->PDDR |= (1UL << pin); in FGPIO_PinInit()
Dfsl_smartcard_phy_tda8035.c240 ((GPIO_Type *)gpio_base[config->vsel0Port])->PDDR |= ((uint32_t)1u << config->vsel0Pin); in SMARTCARD_PHY_Init()
241 ((GPIO_Type *)gpio_base[config->vsel1Port])->PDDR |= ((uint32_t)1u << config->vsel1Pin); in SMARTCARD_PHY_Init()
274 ((GPIO_Type *)gpio_base[config->resetPort])->PDDR |= ((uint32_t)1u << config->resetPin); in SMARTCARD_PHY_Init()
275 ((GPIO_Type *)gpio_base[config->controlPort])->PDDR |= ((uint32_t)1u << config->controlPin); in SMARTCARD_PHY_Init()
279 ((GPIO_Type *)gpio_base[config->irqPort])->PDDR &= ~((uint32_t)1u << config->irqPin); in SMARTCARD_PHY_Init()
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dsystem_MKW22D5.c88 GPIOB->PDDR |= 0x00080000u; /* Set PORTB.19 as output - XCVR RESET pin */ in ExtClk_Setup_HookUp()
89 GPIOC->PDDR |= 0x00000001u; /* Set PORTC.0 as output - XCVR GPIO5 pin */ in ExtClk_Setup_HookUp()
DMKW22D5.h3732 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dsystem_MKW24D5.c88 GPIOB->PDDR |= 0x00080000u; /* Set PORTB.19 as output - XCVR RESET pin */ in ExtClk_Setup_HookUp()
89 GPIOC->PDDR |= 0x00000001u; /* Set PORTC.0 as output - XCVR GPIO5 pin */ in ExtClk_Setup_HookUp()
DMKW24D5.h3732 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/
Dfsl_xcvr.c1880 GPIOC->PDDR |= 0x18; in XCVR_CoexistenceInit()
1884 GPIOC->PDDR |= 0x0A; in XCVR_CoexistenceInit()
1912 GPIOC->PDDR |= 0x12; in XCVR_CoexistenceInit()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h1074 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
1364 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h1954 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
1973 #define FGPIO_PDDR_REG(base) ((base)->PDDR)
2532 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
2551 #define GPIO_PDDR_REG(base) ((base)->PDDR)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h1954 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
1973 #define FGPIO_PDDR_REG(base) ((base)->PDDR)
2532 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
2551 #define GPIO_PDDR_REG(base) ((base)->PDDR)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h1954 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
1973 #define FGPIO_PDDR_REG(base) ((base)->PDDR)
2532 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
2551 #define GPIO_PDDR_REG(base) ((base)->PDDR)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h2214 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
3085 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h2143 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
3014 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h2214 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
3085 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h6113 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h6913 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h7717 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h7722 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h14323 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h12329 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h12612 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h13669 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h12606 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h13609 …__IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ member