| /hal_nxp-2.7.6/mcux/drivers/kinetis/ |
| D | fsl_cmp.h | 249 base->MUXCR |= CMP_MUXCR_PSTM_MASK; in CMP_EnablePassThroughMode()
253 base->MUXCR &= (uint8_t)(~CMP_MUXCR_PSTM_MASK); in CMP_EnablePassThroughMode()
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| D | fsl_cmp.c | 191 uint8_t tmp8 = base->MUXCR; in CMP_SetInputChannels()
195 base->MUXCR = tmp8; in CMP_SetInputChannels()
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| /hal_nxp-2.7.6/mcux/drivers/imx/ |
| D | fsl_cmp.h | 249 base->MUXCR |= CMP_MUXCR_PSTM_MASK; in CMP_EnablePassThroughMode()
253 base->MUXCR &= (uint8_t)(~CMP_MUXCR_PSTM_MASK); in CMP_EnablePassThroughMode()
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| D | fsl_cmp.c | 191 uint8_t tmp8 = base->MUXCR; in CMP_SetInputChannels()
195 base->MUXCR = tmp8; in CMP_SetInputChannels()
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| /hal_nxp-2.7.6/mcux/devices/MKL25Z4/ |
| D | MKL25Z4.h | 608 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW40Z4/ |
| D | MKW40Z4.h | 715 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
734 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
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| /hal_nxp-2.7.6/mcux/devices/MKW20Z4/ |
| D | MKW20Z4.h | 715 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
734 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
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| /hal_nxp-2.7.6/mcux/devices/MKW30Z4/ |
| D | MKW30Z4.h | 715 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
734 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
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| /hal_nxp-2.7.6/mcux/devices/MK22F51212/ |
| D | MK22F51212.h | 870 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW24D5/ |
| D | MKW24D5.h | 1159 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW22D5/ |
| D | MKW22D5.h | 1159 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW31Z4/ |
| D | MKW31Z4.h | 974 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MK64F12/ |
| D | MK64F12.h | 6532 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MKW21Z4/ |
| D | MKW21Z4.h | 903 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MKW41Z4/ |
| D | MKW41Z4.h | 974 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKV56F24/ |
| D | MKV56F24.h | 5930 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MK80F25615/ |
| D | MK80F25615.h | 4788 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKV58F24/ |
| D | MKV58F24.h | 5934 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MK82F25615/ |
| D | MK82F25615.h | 4782 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MK66F18/ |
| D | MK66F18.h | 5583 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 8718 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 8700 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 8544 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 9756 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 9733 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ member
|
