1 /* 2 * Copyright 2017-2020 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 */ 8 9 #ifndef FSL_FTFX_ADAPTER_H 10 #define FSL_FTFX_ADAPTER_H 11 12 /******************************************************************************* 13 * Definitions 14 ******************************************************************************/ 15 16 #define INVALID_REG_MASK (0) 17 #define INVALID_REG_SHIFT (0) 18 #define INVALID_REG_ADDRESS (NULL) 19 #define INVALID_REG_VALUE (0x00U) 20 21 /* @brief Flash register access type defines */ 22 #define FTFx_REG8_ACCESS_TYPE volatile uint8_t * 23 #define FTFx_REG32_ACCESS_TYPE volatile uint32_t * 24 25 /*! 26 * @name Common flash register info defines 27 * @{ 28 */ 29 #if defined(FTFA) 30 #define FTFx FTFA 31 #define FTFx_BASE FTFA_BASE 32 #define FTFx_FSTAT_CCIF_MASK FTFA_FSTAT_CCIF_MASK 33 #define FTFx_FSTAT_CCIF_SHIFT FTFA_FSTAT_CCIF_SHIFT 34 #define FTFx_FSTAT_RDCOLERR_MASK FTFA_FSTAT_RDCOLERR_MASK 35 #define FTFx_FSTAT_ACCERR_MASK FTFA_FSTAT_ACCERR_MASK 36 #define FTFx_FSTAT_FPVIOL_MASK FTFA_FSTAT_FPVIOL_MASK 37 #define FTFx_FSTAT_MGSTAT0_MASK FTFA_FSTAT_MGSTAT0_MASK 38 #define FTFx_FSEC_SEC_MASK FTFA_FSEC_SEC_MASK 39 #define FTFx_FSEC_KEYEN_MASK FTFA_FSEC_KEYEN_MASK 40 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM 41 #define FTFx_FCNFG_RAMRDY_MASK FTFA_FCNFG_RAMRDY_MASK 42 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ 43 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM 44 #define FTFx_FCNFG_EEERDY_MASK FTFA_FCNFG_EEERDY_MASK 45 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ 46 #elif defined(FTFE) 47 #define FTFx FTFE 48 #define FTFx_BASE FTFE_BASE 49 #define FTFx_FSTAT_CCIF_MASK FTFE_FSTAT_CCIF_MASK 50 #define FTFx_FSTAT_CCIF_SHIFT FTFE_FSTAT_CCIF_SHIFT 51 #define FTFx_FSTAT_RDCOLERR_MASK FTFE_FSTAT_RDCOLERR_MASK 52 #define FTFx_FSTAT_ACCERR_MASK FTFE_FSTAT_ACCERR_MASK 53 #define FTFx_FSTAT_FPVIOL_MASK FTFE_FSTAT_FPVIOL_MASK 54 #define FTFx_FSTAT_MGSTAT0_MASK FTFE_FSTAT_MGSTAT0_MASK 55 #define FTFx_FSEC_SEC_MASK FTFE_FSEC_SEC_MASK 56 #define FTFx_FSEC_KEYEN_MASK FTFE_FSEC_KEYEN_MASK 57 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM 58 #define FTFx_FCNFG_RAMRDY_MASK FTFE_FCNFG_RAMRDY_MASK 59 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ 60 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM 61 #define FTFx_FCNFG_EEERDY_MASK FTFE_FCNFG_EEERDY_MASK 62 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ 63 #elif defined(FTFL) 64 #define FTFx FTFL 65 #define FTFx_BASE FTFL_BASE 66 #define FTFx_FSTAT_CCIF_MASK FTFL_FSTAT_CCIF_MASK 67 #define FTFx_FSTAT_CCIF_SHIFT FTFL_FSTAT_CCIF_SHIFT 68 #define FTFx_FSTAT_RDCOLERR_MASK FTFL_FSTAT_RDCOLERR_MASK 69 #define FTFx_FSTAT_ACCERR_MASK FTFL_FSTAT_ACCERR_MASK 70 #define FTFx_FSTAT_FPVIOL_MASK FTFL_FSTAT_FPVIOL_MASK 71 #define FTFx_FSTAT_MGSTAT0_MASK FTFL_FSTAT_MGSTAT0_MASK 72 #define FTFx_FSEC_SEC_MASK FTFL_FSEC_SEC_MASK 73 #define FTFx_FSEC_KEYEN_MASK FTFL_FSEC_KEYEN_MASK 74 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_RAM) && FSL_FEATURE_FLASH_HAS_FLEX_RAM 75 #define FTFx_FCNFG_RAMRDY_MASK FTFL_FCNFG_RAMRDY_MASK 76 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_RAM */ 77 #if defined(FSL_FEATURE_FLASH_HAS_FLEX_NVM) && FSL_FEATURE_FLASH_HAS_FLEX_NVM 78 #define FTFx_FCNFG_EEERDY_MASK FTFL_FCNFG_EEERDY_MASK 79 #endif /* FSL_FEATURE_FLASH_HAS_FLEX_NVM */ 80 #else 81 #error "Unknown flash controller" 82 #endif 83 /*@}*/ 84 85 /*! 86 * @name Common flash register access info defines 87 * @{ 88 */ 89 #define FTFx_FCCOB3_REG (FTFx->FCCOB3) 90 #define FTFx_FCCOB5_REG (FTFx->FCCOB5) 91 #define FTFx_FCCOB6_REG (FTFx->FCCOB6) 92 #define FTFx_FCCOB7_REG (FTFx->FCCOB7) 93 94 #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) 95 #if defined(FTFA_FPROTSL_PROTS_MASK) || defined(FTFE_FPROTSL_PROTS_MASK) || defined(FTFL_FPROTSL_PROTS_MASK) 96 #define FTFx_FLASH1_HAS_INT_PROT_REG (1) 97 #define FTFx_FPROTSH_REG (FTFx->FPROTSH) 98 #define FTFx_FPROTSL_REG (FTFx->FPROTSL) 99 #else 100 #define FTFx_FLASH1_HAS_INT_PROT_REG (0) 101 #endif 102 #endif 103 104 #if defined(FTFA_FPROTH0_PROT_MASK) || defined(FTFE_FPROTH0_PROT_MASK) || defined(FTFL_FPROTH0_PROT_MASK) 105 #define FTFx_FLASH0_HAS_HIGH_PROT_REG (1) 106 #define FTFx_FPROT_HIGH_REG (FTFx->FPROTH3) 107 #define FTFx_FPROTH3_REG (FTFx->FPROTH3) 108 #define FTFx_FPROTH2_REG (FTFx->FPROTH2) 109 #define FTFx_FPROTH1_REG (FTFx->FPROTH1) 110 #define FTFx_FPROTH0_REG (FTFx->FPROTH0) 111 #else 112 #define FTFx_FLASH0_HAS_HIGH_PROT_REG (0) 113 #endif 114 115 #if defined(FTFA_FPROTL0_PROT_MASK) || defined(FTFE_FPROTL0_PROT_MASK) || defined(FTFL_FPROTL0_PROT_MASK) 116 #define FTFx_FPROT_LOW_REG (FTFx->FPROTL3) 117 #define FTFx_FPROTL3_REG (FTFx->FPROTL3) 118 #define FTFx_FPROTL2_REG (FTFx->FPROTL2) 119 #define FTFx_FPROTL1_REG (FTFx->FPROTL1) 120 #define FTFx_FPROTL0_REG (FTFx->FPROTL0) 121 #elif defined(FTFA_FPROT0_PROT_MASK) || defined(FTFE_FPROT0_PROT_MASK) || defined(FTFL_FPROT0_PROT_MASK) 122 #define FTFx_FPROT_LOW_REG (FTFx->FPROT3) 123 #define FTFx_FPROTL3_REG (FTFx->FPROT3) 124 #define FTFx_FPROTL2_REG (FTFx->FPROT2) 125 #define FTFx_FPROTL1_REG (FTFx->FPROT1) 126 #define FTFx_FPROTL0_REG (FTFx->FPROT0) 127 #endif 128 129 #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) 130 #if defined(FTFA_FACSSS_SGSIZE_S_MASK) || defined(FTFE_FACSSS_SGSIZE_S_MASK) || defined(FTFL_FACSSS_SGSIZE_S_MASK) 131 #define FTFx_FLASH1_HAS_INT_XACC_REG (1) 132 #define FTFx_XACCSH_REG (FTFx->XACCSH) 133 #define FTFx_XACCSL_REG (FTFx->XACCSL) 134 #define FTFx_FACSSS_REG (FTFx->FACSSS) 135 #define FTFx_FACSNS_REG (FTFx->FACSNS) 136 #else 137 #define FTFx_FLASH1_HAS_INT_XACC_REG (0) 138 #endif 139 #endif 140 141 #if (defined(FTFA_FACSS_SGSIZE_MASK) || defined(FTFE_FACSS_SGSIZE_MASK) || defined(FTFL_FACSS_SGSIZE_MASK) || \ 142 defined(FTFA_FACSS_SGSIZE_S_MASK) || defined(FTFE_FACSS_SGSIZE_S_MASK) || defined(FTFL_FACSS_SGSIZE_S_MASK)) 143 #define FTFx_FLASH0_HAS_INT_XACC_REG (1) 144 #define FTFx_XACCH3_REG (FTFx->XACCH3) 145 #define FTFx_XACCL3_REG (FTFx->XACCL3) 146 #define FTFx_FACSS_REG (FTFx->FACSS) 147 #define FTFx_FACSN_REG (FTFx->FACSN) 148 #else 149 #define FTFx_FLASH0_HAS_INT_XACC_REG (0) 150 #endif 151 /*@}*/ 152 153 /*! 154 * @brief MCM cache register access info defines. 155 */ 156 #if defined(MCM_PLACR_CFCC_MASK) 157 #define MCM_CACHE_CLEAR_MASK MCM_PLACR_CFCC_MASK 158 #define MCM_CACHE_CLEAR_SHIFT MCM_PLACR_CFCC_SHIFT 159 #if defined(MCM0) 160 #define MCM0_CACHE_REG MCM0->PLACR 161 #elif defined(MCM) && (!defined(MCM1)) 162 #define MCM0_CACHE_REG MCM->PLACR 163 #endif 164 #if defined(MCM1) 165 #define MCM1_CACHE_REG MCM1->PLACR 166 #elif defined(MCM) && (!defined(MCM0)) 167 #define MCM1_CACHE_REG MCM->PLACR 168 #endif 169 #else 170 #define MCM_CACHE_CLEAR_MASK INVALID_REG_MASK 171 #define MCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT 172 #define MCM0_CACHE_REG (INVALID_REG_ADDRESS) 173 #define MCM1_CACHE_REG (INVALID_REG_ADDRESS) 174 #endif 175 176 /*! 177 * @brief FMC cache register access info defines. 178 */ 179 #if defined(FMC_PFB01CR_S_INV_MASK) 180 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_INV_MASK 181 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_INV_SHIFT 182 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR 183 #elif defined(FMC_PFB01CR_S_B_INV_MASK) 184 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB01CR_S_B_INV_MASK 185 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB01CR_S_B_INV_SHIFT 186 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB01CR 187 #elif defined(FMC_PFB0CR_S_INV_MASK) 188 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_INV_MASK 189 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_INV_SHIFT 190 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR 191 #elif defined(FMC_PFB0CR_S_B_INV_MASK) 192 #define FMC_SPECULATION_INVALIDATE_MASK FMC_PFB0CR_S_B_INV_MASK 193 #define FMC_SPECULATION_INVALIDATE_SHIFT FMC_PFB0CR_S_B_INV_SHIFT 194 #define FMC_SPECULATION_INVALIDATE_REG FMC->PFB0CR 195 #else 196 #define FMC_SPECULATION_INVALIDATE_MASK INVALID_REG_MASK 197 #define FMC_SPECULATION_INVALIDATE_SHIFT INVALID_REG_SHIFT 198 #define FMC_SPECULATION_INVALIDATE(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 199 #define FMC_SPECULATION_INVALIDATE_REG (INVALID_REG_ADDRESS) 200 #endif 201 202 #if defined(FMC_PFB01CR_CINV_WAY_MASK) 203 #define FMC_CACHE_CLEAR_MASK FMC_PFB01CR_CINV_WAY_MASK 204 #define FMC_CACHE_CLEAR_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT 205 #define FMC_CACHE_CLEAR(x) FMC_PFB01CR_CINV_WAY(x) 206 #elif defined(FMC_PFB0CR_CINV_WAY_MASK) 207 #define FMC_CACHE_CLEAR_MASK FMC_PFB0CR_CINV_WAY_MASK 208 #define FMC_CACHE_CLEAR_SHIFT FMC_PFB0CR_CINV_WAY_SHIFT 209 #define FMC_CACHE_CLEAR(x) FMC_PFB0CR_CINV_WAY(x) 210 #else 211 #define FMC_CACHE_CLEAR_MASK INVALID_REG_MASK 212 #define FMC_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT 213 #define FMC_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 214 #endif 215 216 #if defined(FMC_PFB01CR_B0DPE_MASK) 217 #define FMC_CACHE_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK 218 #define FMC_CACHE_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK 219 #define FMC_CACHE_REG FMC->PFB01CR 220 #elif defined(FMC_PFB0CR_B0DPE_MASK) 221 #define FMC_CACHE_B0DPE_MASK FMC_PFB0CR_B0DPE_MASK 222 #define FMC_CACHE_B0IPE_MASK FMC_PFB0CR_B0IPE_MASK 223 #define FMC_CACHE_REG FMC->PFB0CR 224 #else 225 #define FMC_CACHE_B0DPE_MASK INVALID_REG_MASK 226 #define FMC_CACHE_B0IPE_MASK INVALID_REG_MASK 227 #define FMC_CACHE_REG (INVALID_REG_ADDRESS) 228 #endif 229 230 /*! 231 * @brief MSCM cache register access info defines. 232 */ 233 #if defined(MSCM_OCMDR_OCM1_MASK) 234 #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCM1_MASK 235 #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCM1_SHIFT 236 #define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCM1(x) 237 #elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) 238 #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR0_OCM1_MASK 239 #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR0_OCM1_SHIFT 240 #define MSCM_SPECULATION_SET(x) MSCM_OCMDR0_OCM1(x) 241 #elif defined(MSCM_OCMDR_OCMC1_MASK) 242 #define MSCM_SPECULATION_SET_MASK MSCM_OCMDR_OCMC1_MASK 243 #define MSCM_SPECULATION_SET_SHIFT MSCM_OCMDR_OCMC1_SHIFT 244 #define MSCM_SPECULATION_SET(x) MSCM_OCMDR_OCMC1(x) 245 #else 246 #define MSCM_SPECULATION_SET_MASK INVALID_REG_MASK 247 #define MSCM_SPECULATION_SET_SHIFT INVALID_REG_SHIFT 248 #define MSCM_SPECULATION_SET(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 249 #endif 250 251 #if defined(MSCM_OCMDR_OCM2_MASK) 252 #define MSCM_CACHE_CLEAR_MASK MSCM_OCMDR_OCM2_MASK 253 #define MSCM_CACHE_CLEAR_SHIFT MSCM_OCMDR_OCM2_SHIFT 254 #define MSCM_CACHE_CLEAR(x) MSCM_OCMDR_OCM2(x) 255 #else 256 #define MSCM_CACHE_CLEAR_MASK INVALID_REG_MASK 257 #define MSCM_CACHE_CLEAR_SHIFT INVALID_REG_SHIFT 258 #define MSCM_CACHE_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << INVALID_REG_SHIFT)) & INVALID_REG_MASK) 259 #endif 260 261 #if defined(MSCM_OCMDR_OCM1_MASK) || defined(MSCM_OCMDR_OCMC1_MASK) 262 #define MSCM_OCMDR0_REG MSCM->OCMDR[0] 263 #define MSCM_OCMDR1_REG MSCM->OCMDR[1] 264 #elif defined(MSCM_OCMDR0_OCM1_MASK) || defined(MSCM_OCMDR1_OCM1_MASK) 265 #define MSCM_OCMDR0_REG MSCM->OCMDR0 266 #define MSCM_OCMDR1_REG MSCM->OCMDR1 267 #else 268 #define MSCM_OCMDR0_REG (INVALID_REG_ADDRESS) 269 #define MSCM_OCMDR1_REG (INVALID_REG_ADDRESS) 270 #endif 271 272 /*! 273 * @brief MSCM prefetch speculation defines. 274 */ 275 #define MSCM_OCMDR_OCMC1_DFDS_MASK (0x10U) 276 #define MSCM_OCMDR_OCMC1_DFCS_MASK (0x20U) 277 #define MSCM_OCMDR_OCMC1_DFDS_SHIFT (4U) 278 #define MSCM_OCMDR_OCMC1_DFCS_SHIFT (5U) 279 280 /*! 281 * @brief SIM PFSIZE register access info defines. 282 */ 283 #if defined(SIM_FCFG1_CORE0_PFSIZE_MASK) 284 #define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_CORE0_PFSIZE_MASK 285 #define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_CORE0_PFSIZE_SHIFT 286 #define SIM_FCFG1_REG SIM->FCFG1 287 #elif defined(SIM_FCFG1_PFSIZE_MASK) 288 #define SIM_FLASH0_PFSIZE_MASK SIM_FCFG1_PFSIZE_MASK 289 #define SIM_FLASH0_PFSIZE_SHIFT SIM_FCFG1_PFSIZE_SHIFT 290 #define SIM_FCFG1_REG SIM->FCFG1 291 #else 292 #define SIM_FLASH0_PFSIZE_MASK INVALID_REG_MASK 293 #define SIM_FLASH0_PFSIZE_SHIFT INVALID_REG_SHIFT 294 #define SIM_FCFG1_REG INVALID_REG_VALUE 295 #endif 296 297 #if defined(SIM_FCFG1_CORE1_PFSIZE_MASK) 298 #define SIM_FLASH1_PFSIZE_MASK SIM_FCFG1_CORE1_PFSIZE_MASK 299 #define SIM_FLASH1_PFSIZE_SHIFT SIM_FCFG1_CORE1_PFSIZE_SHIFT 300 #else 301 #define SIM_FLASH1_PFSIZE_MASK INVALID_REG_MASK 302 #define SIM_FLASH1_PFSIZE_SHIFT INVALID_REG_SHIFT 303 #endif 304 305 /*! 306 * @name Dual core/flash configuration 307 * @{ 308 */ 309 /*! @brief Redefines some flash features. */ 310 #if defined(FSL_FEATURE_FLASH_CURRENT_CORE_ID) 311 #if (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 0u) 312 #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 313 #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT 314 #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE 315 #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE 316 #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE 317 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 318 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 319 #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 320 #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS 321 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT 322 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE 323 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE 324 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE 325 #if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \ 326 defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT) 327 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT 328 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT 329 #else 330 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 331 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 332 #endif 333 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT 334 #elif (FSL_FEATURE_FLASH_CURRENT_CORE_ID == 1u) 335 #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS 336 #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT 337 #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE 338 #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE 339 #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE 340 #if defined(FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT) && \ 341 defined(FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT) 342 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTOR_CMD_ADDRESS_ALIGMENT 343 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_1_SECTION_CMD_ADDRESS_ALIGMENT 344 #else 345 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 346 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 347 #endif 348 #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_1_PROTECTION_REGION_COUNT 349 #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 350 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT 351 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE 352 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE 353 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE 354 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 355 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 356 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 357 #endif 358 #else /* undfine FSL_FEATURE_FLASH_CURRENT_CORE_ID */ 359 #define FLASH0_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 360 #define FLASH0_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT 361 #define FLASH0_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE 362 #define FLASH0_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE 363 #define FLASH0_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE 364 #define FLASH0_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 365 #define FLASH0_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 366 #define FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 367 #if defined(FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH) || defined(FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS) 368 #define FLASH1_FEATURE_PFLASH_START_ADDRESS FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS 369 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT FSL_FEATURE_FLASH_PFLASH_1_BLOCK_COUNT 370 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SIZE 371 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_SECTOR_SIZE 372 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE FSL_FEATURE_FLASH_PFLASH_1_BLOCK_WRITE_UNIT_SIZE 373 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 374 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 375 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT 376 #else /* undfine FSL_FEATURE_FLASH_HAS_MULTIPLE_FLASH or FSL_FEATURE_FLASH_PFLASH_1_START_ADDRESS */ 377 #define FLASH1_FEATURE_PFLASH_START_ADDRESS 0 378 #define FLASH1_FEATURE_PFLASH_BLOCK_COUNT 0 379 #define FLASH1_FEATURE_PFLASH_BLOCK_SIZE 0 380 #define FLASH1_FEATURE_PFLASH_BLOCK_SECTOR_SIZE 0 381 #define FLASH1_FEATURE_PFLASH_BLOCK_WRITE_UNIT_SIZE 0 382 #define FLASH1_FEATURE_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT 0 383 #define FLASH1_FEATURE_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT 0 384 #define FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 0 385 #endif 386 #endif 387 388 #if FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT > FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 389 #define MAX_FLASH_PROT_REGION_COUNT FLASH0_FEATURE_PFLASH_PROTECTION_REGION_COUNT 390 #else 391 #define MAX_FLASH_PROT_REGION_COUNT FLASH1_FEATURE_PFLASH_PROTECTION_REGION_COUNT 392 #endif 393 394 /*@}*/ 395 396 #endif /* FSL_FTFX_ADAPTER_H */ 397
