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Searched refs:MCM_PLACR_EFDS_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_ftfx_cache.c233 MCM0_CACHE_REG |= MCM_PLACR_EFDS_MASK; in FTFx_CACHE_PflashSetPrefetchSpeculation()
237 MCM0_CACHE_REG &= ~MCM_PLACR_EFDS_MASK; in FTFx_CACHE_PflashSetPrefetchSpeculation()
314 if (0U == (value & MCM_PLACR_EFDS_MASK)) in FTFx_CACHE_PflashGetPrefetchSpeculation()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h2256 #define MCM_PLACR_EFDS_MASK (0x4000U) macro
2258 … (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h4533 #define MCM_PLACR_EFDS_MASK (0x4000U) macro
4535 … (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h4650 #define MCM_PLACR_EFDS_MASK 0x4000u macro
4653 …x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_EFDS_SHIFT))&MCM_PLACR_EFDS_MASK)
DMKW40Z4_extension.h14558 #define MCM_RD_PLACR_EFDS(base) ((MCM_PLACR_REG(base) & MCM_PLACR_EFDS_MASK) >> MCM_PLACR_EFDS_SHIF…
14562 #define MCM_WR_PLACR_EFDS(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS(val…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h4462 #define MCM_PLACR_EFDS_MASK (0x4000U) macro
4464 … (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h4533 #define MCM_PLACR_EFDS_MASK (0x4000U) macro
4535 … (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h4650 #define MCM_PLACR_EFDS_MASK 0x4000u macro
4653 …x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_EFDS_SHIFT))&MCM_PLACR_EFDS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h4650 #define MCM_PLACR_EFDS_MASK 0x4000u macro
4653 …x) (((uint32_t)(((uint32_t)(x))<<MCM_PLACR_EFDS_SHIFT))&MCM_PLACR_EFDS_MASK)