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Searched refs:MCG_C6_VDIV0_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dsystem_MKL25Z4.c196 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
Dfsl_clock.c85 #define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
767 MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); in CLOCK_EnablePll0()
DMKL25Z4.h2090 #define MCG_C6_VDIV0_MASK (0x1FU) macro
2092 …x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dsystem_MK22F51212.c200 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
Dfsl_clock.c67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
1057 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
DMK22F51212.h8832 #define MCG_C6_VDIV0_MASK (0x1FU) macro
8868 …x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dsystem_MK64F12.c204 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
Dfsl_clock.c67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
1024 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
DMK64F12.h16723 #define MCG_C6_VDIV0_MASK (0x1FU) macro
16759 …x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dsystem_MKW22D5.c209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
Dfsl_clock.c85 #define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
820 MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); in CLOCK_EnablePll0()
DMKW22D5.h4845 #define MCG_C6_VDIV0_MASK (0x1FU) macro
4847 …x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dsystem_MKW24D5.c209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
Dfsl_clock.c85 #define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
820 MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); in CLOCK_EnablePll0()
DMKW24D5.h4845 #define MCG_C6_VDIV0_MASK (0x1FU) macro
4847 …x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
952 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
DMKV58F24.h16668 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
952 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
DMKV56F24.h15328 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
1066 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
DMK80F25615.h16764 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
1066 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
DMK82F25615.h17511 #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)
1284 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c113 #define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)

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