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Searched refs:MCG_C5_PRDIV0_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dsystem_MKL25Z4.c194 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
Dfsl_clock.c84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMKL25Z4.h2079 #define MCG_C5_PRDIV0_MASK (0x1FU) macro
2081 …) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dsystem_MK22F51212.c198 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
Dfsl_clock.c66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMK22F51212.h8777 #define MCG_C5_PRDIV0_MASK (0x1FU) macro
8813 …) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dsystem_MK64F12.c202 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
Dfsl_clock.c66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMK64F12.h16665 #define MCG_C5_PRDIV0_MASK (0x1FU) macro
16701 …) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dsystem_MKW22D5.c207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
Dfsl_clock.c84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMKW22D5.h4834 #define MCG_C5_PRDIV0_MASK (0x1FU) macro
4836 …) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dsystem_MKW24D5.c207 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U); in SystemCoreClockUpdate()
Dfsl_clock.c84 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMKW24D5.h4834 #define MCG_C5_PRDIV0_MASK (0x1FU) macro
4836 …) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c112 #define MCG_C5_PRDIV0_VAL ((MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMKV58F24.h16662 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMKV56F24.h15322 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMK80F25615.h16758 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)
DMK82F25615.h17505 #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK) macro
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c66 #define MCG_C5_PRDIV0_VAL ((uint8_t)(MCG->C5 & MCG_C5_PRDIV0_MASK) >> MCG_C5_PRDIV0_SHIFT)

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