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Searched refs:MCG_C2_RANGE0_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c73 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
74 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
115 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
87 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
Dsystem_MKL25Z4.c144 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) { in SystemCoreClockUpdate()
DMKL25Z4.h2052 #define MCG_C2_RANGE0_MASK (0x30U) macro
2054 …) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
2191 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
87 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
Dsystem_MKW22D5.c157 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
DMKW22D5.h4807 #define MCG_C2_RANGE0_MASK (0x30U) macro
4809 …) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
4960 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
87 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
Dsystem_MKW24D5.c157 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
DMKW24D5.h4807 #define MCG_C2_RANGE0_MASK (0x30U) macro
4809 …) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK)
4960 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
DMK22F51212.h15328 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
DMK64F12.h26225 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
DMK66F18.h30490 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro