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Searched refs:LPTMR_CSR_TPS_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h1930 #define LPTMR_CSR_TPS_MASK (0x30U) macro
1932 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h7903 #define LPTMR_CSR_TPS_MASK (0x30U) macro
7911 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h4685 #define LPTMR_CSR_TPS_MASK (0x30U) macro
4687 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h9304 #define LPTMR_CSR_TPS_MASK (0x30U) macro
9312 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h4685 #define LPTMR_CSR_TPS_MASK (0x30U) macro
4687 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h10108 #define LPTMR_CSR_TPS_MASK (0x30U) macro
10116 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h10113 #define LPTMR_CSR_TPS_MASK (0x30U) macro
10121 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h3658 #define LPTMR_CSR_TPS_MASK (0x30U) macro
3660 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h16357 #define LPTMR_CSR_TPS_MASK (0x30U) macro
16365 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h3400 #define LPTMR_CSR_TPS_MASK 0x30u macro
3403 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
DMKW40Z4_extension.h9999 #define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
10003 #define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h3587 #define LPTMR_CSR_TPS_MASK (0x30U) macro
3589 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h3658 #define LPTMR_CSR_TPS_MASK (0x30U) macro
3660 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h3400 #define LPTMR_CSR_TPS_MASK 0x30u macro
3403 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h3400 #define LPTMR_CSR_TPS_MASK 0x30u macro
3403 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h14802 #define LPTMR_CSR_TPS_MASK (0x30U) macro
14810 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h15443 #define LPTMR_CSR_TPS_MASK (0x30U) macro
15451 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h16142 #define LPTMR_CSR_TPS_MASK (0x30U) macro
16150 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h15437 #define LPTMR_CSR_TPS_MASK (0x30U) macro
15445 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h16132 #define LPTMR_CSR_TPS_MASK (0x30U) macro
16140 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)