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Searched refs:LPTMR_CSR_TPP_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h1927 #define LPTMR_CSR_TPP_MASK (0x8U) macro
1929 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h7896 #define LPTMR_CSR_TPP_MASK (0x8U) macro
7902 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h4682 #define LPTMR_CSR_TPP_MASK (0x8U) macro
4684 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h9297 #define LPTMR_CSR_TPP_MASK (0x8U) macro
9303 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h4682 #define LPTMR_CSR_TPP_MASK (0x8U) macro
4684 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h10101 #define LPTMR_CSR_TPP_MASK (0x8U) macro
10107 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h10106 #define LPTMR_CSR_TPP_MASK (0x8U) macro
10112 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h3655 #define LPTMR_CSR_TPP_MASK (0x8U) macro
3657 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h16349 #define LPTMR_CSR_TPP_MASK (0x8U) macro
16355 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h3396 #define LPTMR_CSR_TPP_MASK 0x8u macro
3399 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
DMKW40Z4_extension.h9975 #define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
9979 #define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h3584 #define LPTMR_CSR_TPP_MASK (0x8U) macro
3586 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h3655 #define LPTMR_CSR_TPP_MASK (0x8U) macro
3657 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h3396 #define LPTMR_CSR_TPP_MASK 0x8u macro
3399 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h3396 #define LPTMR_CSR_TPP_MASK 0x8u macro
3399 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPP_SHIFT))&LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h14795 #define LPTMR_CSR_TPP_MASK (0x8U) macro
14801 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h15436 #define LPTMR_CSR_TPP_MASK (0x8U) macro
15442 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h16135 #define LPTMR_CSR_TPP_MASK (0x8U) macro
16141 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h15430 #define LPTMR_CSR_TPP_MASK (0x8U) macro
15436 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h16125 #define LPTMR_CSR_TPP_MASK (0x8U) macro
16131 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)