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Searched refs:LPTMR_CSR_TMS_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h1921 #define LPTMR_CSR_TMS_MASK (0x2U) macro
1923 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h7882 #define LPTMR_CSR_TMS_MASK (0x2U) macro
7888 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h4676 #define LPTMR_CSR_TMS_MASK (0x2U) macro
4678 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h9283 #define LPTMR_CSR_TMS_MASK (0x2U) macro
9289 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h4676 #define LPTMR_CSR_TMS_MASK (0x2U) macro
4678 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h10087 #define LPTMR_CSR_TMS_MASK (0x2U) macro
10093 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h10092 #define LPTMR_CSR_TMS_MASK (0x2U) macro
10098 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h3649 #define LPTMR_CSR_TMS_MASK (0x2U) macro
3651 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h16333 #define LPTMR_CSR_TMS_MASK (0x2U) macro
16339 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h3388 #define LPTMR_CSR_TMS_MASK 0x2u macro
3391 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
DMKW40Z4_extension.h9932 #define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
9936 #define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h3578 #define LPTMR_CSR_TMS_MASK (0x2U) macro
3580 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h3649 #define LPTMR_CSR_TMS_MASK (0x2U) macro
3651 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h3388 #define LPTMR_CSR_TMS_MASK 0x2u macro
3391 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h3388 #define LPTMR_CSR_TMS_MASK 0x2u macro
3391 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TMS_SHIFT))&LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h14781 #define LPTMR_CSR_TMS_MASK (0x2U) macro
14787 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h15422 #define LPTMR_CSR_TMS_MASK (0x2U) macro
15428 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h16121 #define LPTMR_CSR_TMS_MASK (0x2U) macro
16127 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h15416 #define LPTMR_CSR_TMS_MASK (0x2U) macro
15422 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h16111 #define LPTMR_CSR_TMS_MASK (0x2U) macro
16117 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)