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Searched refs:LPTMR_CSR_TEN_MASK (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_lptmr.h345 reg |= LPTMR_CSR_TEN_MASK; in LPTMR_StartTimer()
362 reg &= ~LPTMR_CSR_TEN_MASK; in LPTMR_StopTimer()
Dfsl_lptmr.c115 base->CSR &= ~LPTMR_CSR_TEN_MASK; in LPTMR_Deinit()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h1918 #define LPTMR_CSR_TEN_MASK (0x1U) macro
1920 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h7875 #define LPTMR_CSR_TEN_MASK (0x1U) macro
7881 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h4673 #define LPTMR_CSR_TEN_MASK (0x1U) macro
4675 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h9276 #define LPTMR_CSR_TEN_MASK (0x1U) macro
9282 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h4673 #define LPTMR_CSR_TEN_MASK (0x1U) macro
4675 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h10080 #define LPTMR_CSR_TEN_MASK (0x1U) macro
10086 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h10085 #define LPTMR_CSR_TEN_MASK (0x1U) macro
10091 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h3646 #define LPTMR_CSR_TEN_MASK (0x1U) macro
3648 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h16325 #define LPTMR_CSR_TEN_MASK (0x1U) macro
16331 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h3384 #define LPTMR_CSR_TEN_MASK 0x1u macro
3387 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
DMKW40Z4_extension.h9912 #define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
9916 #define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h3575 #define LPTMR_CSR_TEN_MASK (0x1U) macro
3577 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h3646 #define LPTMR_CSR_TEN_MASK (0x1U) macro
3648 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h3384 #define LPTMR_CSR_TEN_MASK 0x1u macro
3387 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h3384 #define LPTMR_CSR_TEN_MASK 0x1u macro
3387 …(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TEN_SHIFT))&LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h14774 #define LPTMR_CSR_TEN_MASK (0x1U) macro
14780 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h15415 #define LPTMR_CSR_TEN_MASK (0x1U) macro
15421 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h16114 #define LPTMR_CSR_TEN_MASK (0x1U) macro
16120 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h15409 #define LPTMR_CSR_TEN_MASK (0x1U) macro
15415 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h16104 #define LPTMR_CSR_TEN_MASK (0x1U) macro
16110 … (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)