/hal_nxp-2.7.6/mcux/devices/MKL25Z4/ |
D | MKL25Z4.h | 1969 #define LPTMR0_BASE (0x40040000u) macro 1971 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 1973 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MK22F51212/ |
D | MK22F51212.h | 7991 #define LPTMR0_BASE (0x40040000u) macro 7993 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 7995 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW24D5/ |
D | MKW24D5.h | 4724 #define LPTMR0_BASE (0x40040000u) macro 4726 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 4728 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKE14F16/ |
D | MKE14F16.h | 9399 #define LPTMR0_BASE (0x40040000u) macro 9401 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 9403 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW22D5/ |
D | MKW22D5.h | 4724 #define LPTMR0_BASE (0x40040000u) macro 4726 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 4728 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKE16F16/ |
D | MKE16F16.h | 10203 #define LPTMR0_BASE (0x40040000u) macro 10205 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 10207 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKE18F16/ |
D | MKE18F16.h | 10208 #define LPTMR0_BASE (0x40040000u) macro 10210 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 10212 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW31Z4/ |
D | MKW31Z4.h | 3697 #define LPTMR0_BASE (0x40040000u) macro 3699 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 3701 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MK64F12/ |
D | MK64F12.h | 16456 #define LPTMR0_BASE (0x40040000u) macro 16458 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 16460 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW40Z4/ |
D | MKW40Z4.h | 3443 #define LPTMR0_BASE (0x40040000u) macro 3445 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 3448 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW21Z4/ |
D | MKW21Z4.h | 3626 #define LPTMR0_BASE (0x40040000u) macro 3628 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 3630 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW41Z4/ |
D | MKW41Z4.h | 3697 #define LPTMR0_BASE (0x40040000u) macro 3699 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 3701 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW20Z4/ |
D | MKW20Z4.h | 3443 #define LPTMR0_BASE (0x40040000u) macro 3445 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 3448 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKW30Z4/ |
D | MKW30Z4.h | 3443 #define LPTMR0_BASE (0x40040000u) macro 3445 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 3448 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKV56F24/ |
D | MKV56F24.h | 14890 #define LPTMR0_BASE (0x40040000u) macro 14892 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 14894 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MK80F25615/ |
D | MK80F25615.h | 15531 #define LPTMR0_BASE (0x40040000u) macro 15533 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 15539 #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE }
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/hal_nxp-2.7.6/mcux/devices/MKV58F24/ |
D | MKV58F24.h | 16230 #define LPTMR0_BASE (0x40040000u) macro 16232 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 16234 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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/hal_nxp-2.7.6/mcux/devices/MK82F25615/ |
D | MK82F25615.h | 15525 #define LPTMR0_BASE (0x40040000u) macro 15527 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 15533 #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE }
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/hal_nxp-2.7.6/mcux/devices/MK66F18/ |
D | MK66F18.h | 16220 #define LPTMR0_BASE (0x40040000u) macro 16222 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 16224 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
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