1 /*
2 * Copyright 2016 Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_IOMUXC_H_
10 #define _FSL_IOMUXC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup iomuxc_driver
16 * @{
17 */
18
19 /*! @file */
20
21 /*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24 /* Component ID definition, used by tools. */
25 #ifndef FSL_COMPONENT_ID
26 #define FSL_COMPONENT_ID "platform.drivers.iomuxc"
27 #endif
28
29 /*! @name Driver version */
30 /*@{*/
31 /*! @brief IOMUXC driver version 2.0.3. */
32 #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
33 /*@}*/
34
35 /*!
36 * @name Pin function ID
37 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
38 *
39 * @{
40 */
41 #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8000U, 0x0U, 0, 0, 0x400A8010U
42 #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8010U
43
44 #define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A8004U
45
46 #define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8008U
47
48 #define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A800CU
49
50 #define IOMUXC_GPIO_AD_14_LPI2C1_SCL 0x401F8010U, 0x0U, 0x401F81C0U, 0x0U, 0x401F80C0U
51 #define IOMUXC_GPIO_AD_14_LPUART3_CTS_B 0x401F8010U, 0x1U, 0, 0, 0x401F80C0U
52 #define IOMUXC_GPIO_AD_14_KPP_COL00 0x401F8010U, 0x2U, 0x401F819CU, 0x0U, 0x401F80C0U
53 #define IOMUXC_GPIO_AD_14_LPUART4_CTS_B 0x401F8010U, 0x3U, 0, 0, 0x401F80C0U
54 #define IOMUXC_GPIO_AD_14_FLEXIO1_IO26 0x401F8010U, 0x4U, 0, 0, 0x401F80C0U
55 #define IOMUXC_GPIO_AD_14_GPIOMUX_IO28 0x401F8010U, 0x5U, 0, 0, 0x401F80C0U
56 #define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x401F8010U, 0x6U, 0, 0, 0x401F80C0U
57 #define IOMUXC_GPIO_AD_14_XBAR1_INOUT02 0x401F8010U, 0x7U, 0, 0, 0x401F80C0U
58
59 #define IOMUXC_GPIO_AD_13_LPI2C1_SDA 0x401F8014U, 0x0U, 0x401F81C4U, 0x0U, 0x401F80C4U
60 #define IOMUXC_GPIO_AD_13_LPUART3_RTS_B 0x401F8014U, 0x1U, 0, 0, 0x401F80C4U
61 #define IOMUXC_GPIO_AD_13_KPP_ROW00 0x401F8014U, 0x2U, 0x401F81ACU, 0x0U, 0x401F80C4U
62 #define IOMUXC_GPIO_AD_13_LPUART4_RTS_B 0x401F8014U, 0x3U, 0, 0, 0x401F80C4U
63 #define IOMUXC_GPIO_AD_13_FLEXIO1_IO25 0x401F8014U, 0x4U, 0, 0, 0x401F80C4U
64 #define IOMUXC_GPIO_AD_13_GPIOMUX_IO27 0x401F8014U, 0x5U, 0, 0, 0x401F80C4U
65 #define IOMUXC_GPIO_AD_13_ARM_NMI 0x401F8014U, 0x6U, 0x401F8210U, 0x0U, 0x401F80C4U
66 #define IOMUXC_GPIO_AD_13_JTAG_TMS 0x401F8014U, 0x7U, 0, 0, 0x401F80C4U
67
68 #define IOMUXC_GPIO_AD_12_LPSPI2_SCK 0x401F8018U, 0x0U, 0x401F81E4U, 0x0U, 0x401F80C8U
69 #define IOMUXC_GPIO_AD_12_FLEXPWM1_PWM0_X 0x401F8018U, 0x1U, 0, 0, 0x401F80C8U
70 #define IOMUXC_GPIO_AD_12_KPP_COL01 0x401F8018U, 0x2U, 0x401F81A0U, 0x0U, 0x401F80C8U
71 #define IOMUXC_GPIO_AD_12_PIT_TRIGGER01 0x401F8018U, 0x3U, 0, 0, 0x401F80C8U
72 #define IOMUXC_GPIO_AD_12_FLEXIO1_IO24 0x401F8018U, 0x4U, 0, 0, 0x401F80C8U
73 #define IOMUXC_GPIO_AD_12_GPIOMUX_IO26 0x401F8018U, 0x5U, 0, 0, 0x401F80C8U
74 #define IOMUXC_GPIO_AD_12_USB_OTG1_PWR 0x401F8018U, 0x6U, 0, 0, 0x401F80C8U
75 #define IOMUXC_GPIO_AD_12_JTAG_TCK 0x401F8018U, 0x7U, 0, 0, 0x401F80C8U
76
77 #define IOMUXC_GPIO_AD_11_LPSPI2_PCS0 0x401F801CU, 0x0U, 0x401F81E0U, 0x0U, 0x401F80CCU
78 #define IOMUXC_GPIO_AD_11_FLEXPWM1_PWM1_X 0x401F801CU, 0x1U, 0, 0, 0x401F80CCU
79 #define IOMUXC_GPIO_AD_11_KPP_ROW01 0x401F801CU, 0x2U, 0x401F81B0U, 0x0U, 0x401F80CCU
80 #define IOMUXC_GPIO_AD_11_PIT_TRIGGER02 0x401F801CU, 0x3U, 0, 0, 0x401F80CCU
81 #define IOMUXC_GPIO_AD_11_FLEXIO1_IO23 0x401F801CU, 0x4U, 0, 0, 0x401F80CCU
82 #define IOMUXC_GPIO_AD_11_GPIOMUX_IO25 0x401F801CU, 0x5U, 0, 0, 0x401F80CCU
83 #define IOMUXC_GPIO_AD_11_WDOG1_B 0x401F801CU, 0x6U, 0, 0, 0x401F80CCU
84 #define IOMUXC_GPIO_AD_11_JTAG_MOD 0x401F801CU, 0x7U, 0, 0, 0x401F80CCU
85
86 #define IOMUXC_GPIO_AD_10_LPSPI2_SDO 0x401F8020U, 0x0U, 0x401F81ECU, 0x0U, 0x401F80D0U
87 #define IOMUXC_GPIO_AD_10_FLEXPWM1_PWM2_X 0x401F8020U, 0x1U, 0, 0, 0x401F80D0U
88 #define IOMUXC_GPIO_AD_10_KPP_COL02 0x401F8020U, 0x2U, 0x401F81A4U, 0x0U, 0x401F80D0U
89 #define IOMUXC_GPIO_AD_10_PIT_TRIGGER03 0x401F8020U, 0x3U, 0, 0, 0x401F80D0U
90 #define IOMUXC_GPIO_AD_10_FLEXIO1_IO22 0x401F8020U, 0x4U, 0, 0, 0x401F80D0U
91 #define IOMUXC_GPIO_AD_10_GPIOMUX_IO24 0x401F8020U, 0x5U, 0, 0, 0x401F80D0U
92 #define IOMUXC_GPIO_AD_10_USB_OTG1_ID 0x401F8020U, 0x6U, 0x401F8170U, 0x0U, 0x401F80D0U
93 #define IOMUXC_GPIO_AD_10_JTAG_TDI 0x401F8020U, 0x7U, 0, 0, 0x401F80D0U
94
95 #define IOMUXC_GPIO_AD_09_LPSPI2_SDI 0x401F8024U, 0x0U, 0x401F81E8U, 0x0U, 0x401F80D4U
96 #define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x401F8024U, 0x1U, 0, 0, 0x401F80D4U
97 #define IOMUXC_GPIO_AD_09_KPP_ROW02 0x401F8024U, 0x2U, 0x401F81B4U, 0x0U, 0x401F80D4U
98 #define IOMUXC_GPIO_AD_09_ARM_TRACE_SWO 0x401F8024U, 0x3U, 0, 0, 0x401F80D4U
99 #define IOMUXC_GPIO_AD_09_FLEXIO1_IO21 0x401F8024U, 0x4U, 0, 0, 0x401F80D4U
100 #define IOMUXC_GPIO_AD_09_GPIOMUX_IO23 0x401F8024U, 0x5U, 0, 0, 0x401F80D4U
101 #define IOMUXC_GPIO_AD_09_REF_32K_OUT 0x401F8024U, 0x6U, 0, 0, 0x401F80D4U
102 #define IOMUXC_GPIO_AD_09_JTAG_TDO 0x401F8024U, 0x7U, 0, 0, 0x401F80D4U
103
104 #define IOMUXC_GPIO_AD_08_LPI2C2_SCL 0x401F8028U, 0x0U, 0x401F81C8U, 0x0U, 0x401F80D8U
105 #define IOMUXC_GPIO_AD_08_LPUART3_TXD 0x401F8028U, 0x1U, 0x401F8204U, 0x0U, 0x401F80D8U
106 #define IOMUXC_GPIO_AD_08_ARM_CM7_TXEV 0x401F8028U, 0x2U, 0, 0, 0x401F80D8U
107 #define IOMUXC_GPIO_AD_08_LPUART2_CTS_B 0x401F8028U, 0x3U, 0, 0, 0x401F80D8U
108 #define IOMUXC_GPIO_AD_08_GPT2_COMPARE3 0x401F8028U, 0x4U, 0, 0, 0x401F80D8U
109 #define IOMUXC_GPIO_AD_08_GPIOMUX_IO22 0x401F8028U, 0x5U, 0, 0, 0x401F80D8U
110 #define IOMUXC_GPIO_AD_08_EWM_OUT_B 0x401F8028U, 0x6U, 0, 0, 0x401F80D8U
111 #define IOMUXC_GPIO_AD_08_JTAG_TRSTB 0x401F8028U, 0x7U, 0, 0, 0x401F80D8U
112
113 #define IOMUXC_GPIO_AD_07_LPI2C2_SDA 0x401F802CU, 0x0U, 0x401F81CCU, 0x0U, 0x401F80DCU
114 #define IOMUXC_GPIO_AD_07_LPUART3_RXD 0x401F802CU, 0x1U, 0x401F8200U, 0x0U, 0x401F80DCU
115 #define IOMUXC_GPIO_AD_07_ARM_CM7_RXEV 0x401F802CU, 0x2U, 0x401F8220U, 0x0U, 0x401F80DCU
116 #define IOMUXC_GPIO_AD_07_LPUART2_RTS_B 0x401F802CU, 0x3U, 0, 0, 0x401F80DCU
117 #define IOMUXC_GPIO_AD_07_GPT2_CAPTURE2 0x401F802CU, 0x4U, 0, 0, 0x401F80DCU
118 #define IOMUXC_GPIO_AD_07_GPIOMUX_IO21 0x401F802CU, 0x5U, 0, 0, 0x401F80DCU
119 #define IOMUXC_GPIO_AD_07_OCOTP_FUSE_LATCHED 0x401F802CU, 0x6U, 0, 0, 0x401F80DCU
120 #define IOMUXC_GPIO_AD_07_XBAR1_INOUT03 0x401F802CU, 0x7U, 0, 0, 0x401F80DCU
121
122 #define IOMUXC_GPIO_AD_06_LPSPI1_SCK 0x401F8030U, 0x0U, 0x401F81D4U, 0x0U, 0x401F80E0U
123 #define IOMUXC_GPIO_AD_06_PIT_TRIGGER00 0x401F8030U, 0x1U, 0, 0, 0x401F80E0U
124 #define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM3_A 0x401F8030U, 0x2U, 0x401F8180U, 0x0U, 0x401F80E0U
125 #define IOMUXC_GPIO_AD_06_KPP_COL01 0x401F8030U, 0x3U, 0x401F81A0U, 0x1U, 0x401F80E0U
126 #define IOMUXC_GPIO_AD_06_GPT2_COMPARE2 0x401F8030U, 0x4U, 0, 0, 0x401F80E0U
127 #define IOMUXC_GPIO_AD_06_GPIOMUX_IO20 0x401F8030U, 0x5U, 0, 0, 0x401F80E0U
128 #define IOMUXC_GPIO_AD_06_LPI2C1_HREQ 0x401F8030U, 0x6U, 0x401F81BCU, 0x0U, 0x401F80E0U
129
130 #define IOMUXC_GPIO_AD_05_LPSPI1_PCS0 0x401F8034U, 0x0U, 0x401F81D0U, 0x0U, 0x401F80E4U
131 #define IOMUXC_GPIO_AD_05_PIT_TRIGGER01 0x401F8034U, 0x1U, 0, 0, 0x401F80E4U
132 #define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM3_B 0x401F8034U, 0x2U, 0x401F8190U, 0x0U, 0x401F80E4U
133 #define IOMUXC_GPIO_AD_05_KPP_ROW01 0x401F8034U, 0x3U, 0x401F81B0U, 0x1U, 0x401F80E4U
134 #define IOMUXC_GPIO_AD_05_GPT2_CAPTURE1 0x401F8034U, 0x4U, 0, 0, 0x401F80E4U
135 #define IOMUXC_GPIO_AD_05_GPIOMUX_IO19 0x401F8034U, 0x5U, 0, 0, 0x401F80E4U
136
137 #define IOMUXC_GPIO_AD_04_LPSPI1_SDO 0x401F8038U, 0x0U, 0x401F81DCU, 0x0U, 0x401F80E8U
138 #define IOMUXC_GPIO_AD_04_PIT_TRIGGER02 0x401F8038U, 0x1U, 0, 0, 0x401F80E8U
139 #define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x401F8038U, 0x2U, 0x401F817CU, 0x0U, 0x401F80E8U
140 #define IOMUXC_GPIO_AD_04_KPP_COL02 0x401F8038U, 0x3U, 0x401F81A4U, 0x1U, 0x401F80E8U
141 #define IOMUXC_GPIO_AD_04_GPT2_COMPARE1 0x401F8038U, 0x4U, 0, 0, 0x401F80E8U
142 #define IOMUXC_GPIO_AD_04_GPIOMUX_IO18 0x401F8038U, 0x5U, 0, 0, 0x401F80E8U
143 #define IOMUXC_GPIO_AD_04_SNVS_VIO_5_CTL 0x401F8038U, 0x6U, 0, 0, 0x401F80E8U
144
145 #define IOMUXC_GPIO_AD_03_LPSPI1_SDI 0x401F803CU, 0x0U, 0x401F81D8U, 0x0U, 0x401F80ECU
146 #define IOMUXC_GPIO_AD_03_PIT_TRIGGER03 0x401F803CU, 0x1U, 0, 0, 0x401F80ECU
147 #define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM2_B 0x401F803CU, 0x2U, 0x401F818CU, 0x0U, 0x401F80ECU
148 #define IOMUXC_GPIO_AD_03_KPP_ROW02 0x401F803CU, 0x3U, 0x401F81B4U, 0x1U, 0x401F80ECU
149 #define IOMUXC_GPIO_AD_03_GPT2_CLK 0x401F803CU, 0x4U, 0, 0, 0x401F80ECU
150 #define IOMUXC_GPIO_AD_03_GPIOMUX_IO17 0x401F803CU, 0x5U, 0, 0, 0x401F80ECU
151 #define IOMUXC_GPIO_AD_03_SNVS_VIO_5_B 0x401F803CU, 0x6U, 0, 0, 0x401F80ECU
152 #define IOMUXC_GPIO_AD_03_JTAG_DE_B 0x401F803CU, 0x7U, 0, 0, 0x401F80ECU
153
154 #define IOMUXC_GPIO_AD_02_LPUART4_TXD 0x401F8040U, 0x0U, 0x401F820CU, 0x0U, 0x401F80F0U
155 #define IOMUXC_GPIO_AD_02_LPSPI1_PCS1 0x401F8040U, 0x1U, 0, 0, 0x401F80F0U
156 #define IOMUXC_GPIO_AD_02_WDOG2_B 0x401F8040U, 0x2U, 0, 0, 0x401F80F0U
157 #define IOMUXC_GPIO_AD_02_LPI2C2_SCL 0x401F8040U, 0x3U, 0x401F81C8U, 0x1U, 0x401F80F0U
158 #define IOMUXC_GPIO_AD_02_MQS_RIGHT 0x401F8040U, 0x4U, 0, 0, 0x401F80F0U
159 #define IOMUXC_GPIO_AD_02_GPIOMUX_IO16 0x401F8040U, 0x5U, 0, 0, 0x401F80F0U
160 #define IOMUXC_GPIO_AD_02_ARM_TRACE_CLK 0x401F8040U, 0x7U, 0, 0, 0x401F80F0U
161
162 #define IOMUXC_GPIO_AD_01_LPUART4_RXD 0x401F8044U, 0x0U, 0x401F8208U, 0x0U, 0x401F80F4U
163 #define IOMUXC_GPIO_AD_01_LPSPI2_PCS1 0x401F8044U, 0x1U, 0, 0, 0x401F80F4U
164 #define IOMUXC_GPIO_AD_01_WDOG1_ANY 0x401F8044U, 0x2U, 0, 0, 0x401F80F4U
165 #define IOMUXC_GPIO_AD_01_LPI2C2_SDA 0x401F8044U, 0x3U, 0x401F81CCU, 0x1U, 0x401F80F4U
166 #define IOMUXC_GPIO_AD_01_MQS_LEFT 0x401F8044U, 0x4U, 0, 0, 0x401F80F4U
167 #define IOMUXC_GPIO_AD_01_GPIOMUX_IO15 0x401F8044U, 0x5U, 0, 0, 0x401F80F4U
168 #define IOMUXC_GPIO_AD_01_USB_OTG1_OC 0x401F8044U, 0x6U, 0x401F821CU, 0x0U, 0x401F80F4U
169 #define IOMUXC_GPIO_AD_01_ARM_TRACE_SWO 0x401F8044U, 0x7U, 0, 0, 0x401F80F4U
170
171 #define IOMUXC_GPIO_AD_00_LPUART2_TXD 0x401F8048U, 0x0U, 0x401F81FCU, 0x0U, 0x401F80F8U
172 #define IOMUXC_GPIO_AD_00_LPSPI1_PCS2 0x401F8048U, 0x1U, 0, 0, 0x401F80F8U
173 #define IOMUXC_GPIO_AD_00_KPP_COL03 0x401F8048U, 0x2U, 0x401F81A8U, 0x0U, 0x401F80F8U
174 #define IOMUXC_GPIO_AD_00_USB_OTG1_PWR 0x401F8048U, 0x3U, 0, 0, 0x401F80F8U
175 #define IOMUXC_GPIO_AD_00_FLEXIO1_IO20 0x401F8048U, 0x4U, 0, 0, 0x401F80F8U
176 #define IOMUXC_GPIO_AD_00_GPIOMUX_IO14 0x401F8048U, 0x5U, 0, 0, 0x401F80F8U
177 #define IOMUXC_GPIO_AD_00_ARM_NMI 0x401F8048U, 0x6U, 0x401F8210U, 0x1U, 0x401F80F8U
178 #define IOMUXC_GPIO_AD_00_ARM_TRACE0 0x401F8048U, 0x7U, 0, 0, 0x401F80F8U
179
180 #define IOMUXC_GPIO_SD_14_FLEXSPI_A_DQS 0x401F804CU, 0x0U, 0x401F8194U, 0x0U, 0x401F80FCU
181 #define IOMUXC_GPIO_SD_14_FLEXSPI_B_DQS 0x401F804CU, 0x1U, 0x401F8198U, 0x0U, 0x401F80FCU
182
183 #define IOMUXC_GPIO_SD_13_FLEXSPI_B_SCLK 0x401F8050U, 0x0U, 0, 0, 0x401F8100U
184 #define IOMUXC_GPIO_SD_13_SAI3_RX_BCLK 0x401F8050U, 0x1U, 0, 0, 0x401F8100U
185 #define IOMUXC_GPIO_SD_13_ARM_CM7_TXEV 0x401F8050U, 0x2U, 0, 0, 0x401F8100U
186 #define IOMUXC_GPIO_SD_13_CCM_PMIC_RDY 0x401F8050U, 0x3U, 0, 0, 0x401F8100U
187 #define IOMUXC_GPIO_SD_13_FLEXIO1_IO19 0x401F8050U, 0x4U, 0, 0, 0x401F8100U
188 #define IOMUXC_GPIO_SD_13_GPIO2_IO13 0x401F8050U, 0x5U, 0, 0, 0x401F8100U
189 #define IOMUXC_GPIO_SD_13_SRC_BT_CFG03 0x401F8050U, 0x6U, 0, 0, 0x401F8100U
190
191 #define IOMUXC_GPIO_SD_12_FLEXSPI_A_DQS 0x401F8054U, 0x0U, 0x401F8194U, 0x1U, 0x401F8104U
192 #define IOMUXC_GPIO_SD_12_LPSPI2_PCS0 0x401F8054U, 0x1U, 0x401F81E0U, 0x1U, 0x401F8104U
193 #define IOMUXC_GPIO_SD_12_LPUART1_TXD 0x401F8054U, 0x2U, 0x401F81F4U, 0x0U, 0x401F8104U
194 #define IOMUXC_GPIO_SD_12_FLEXIO1_IO18 0x401F8054U, 0x4U, 0, 0, 0x401F8104U
195 #define IOMUXC_GPIO_SD_12_GPIO2_IO12 0x401F8054U, 0x5U, 0, 0, 0x401F8104U
196 #define IOMUXC_GPIO_SD_12_WDOG2_RST_B_DEB 0x401F8054U, 0x6U, 0, 0, 0x401F8104U
197
198 #define IOMUXC_GPIO_SD_11_FLEXSPI_A_DATA3 0x401F8058U, 0x0U, 0, 0, 0x401F8108U
199 #define IOMUXC_GPIO_SD_11_LPSPI2_SCK 0x401F8058U, 0x1U, 0x401F81E4U, 0x1U, 0x401F8108U
200 #define IOMUXC_GPIO_SD_11_LPUART1_RXD 0x401F8058U, 0x2U, 0x401F81F0U, 0x0U, 0x401F8108U
201 #define IOMUXC_GPIO_SD_11_FLEXIO1_IO17 0x401F8058U, 0x4U, 0, 0, 0x401F8108U
202 #define IOMUXC_GPIO_SD_11_GPIO2_IO11 0x401F8058U, 0x5U, 0, 0, 0x401F8108U
203 #define IOMUXC_GPIO_SD_11_WDOG1_RST_B_DEB 0x401F8058U, 0x6U, 0, 0, 0x401F8108U
204
205 #define IOMUXC_GPIO_SD_10_FLEXSPI_A_SCLK 0x401F805CU, 0x0U, 0, 0, 0x401F810CU
206 #define IOMUXC_GPIO_SD_10_LPSPI2_SDO 0x401F805CU, 0x1U, 0x401F81ECU, 0x1U, 0x401F810CU
207 #define IOMUXC_GPIO_SD_10_LPUART2_TXD 0x401F805CU, 0x2U, 0x401F81FCU, 0x1U, 0x401F810CU
208 #define IOMUXC_GPIO_SD_10_FLEXIO1_IO16 0x401F805CU, 0x4U, 0, 0, 0x401F810CU
209 #define IOMUXC_GPIO_SD_10_GPIO2_IO10 0x401F805CU, 0x5U, 0, 0, 0x401F810CU
210
211 #define IOMUXC_GPIO_SD_09_FLEXSPI_A_DATA0 0x401F8060U, 0x0U, 0, 0, 0x401F8110U
212 #define IOMUXC_GPIO_SD_09_LPSPI2_SDI 0x401F8060U, 0x1U, 0x401F81E8U, 0x1U, 0x401F8110U
213 #define IOMUXC_GPIO_SD_09_LPUART2_RXD 0x401F8060U, 0x2U, 0x401F81F8U, 0x0U, 0x401F8110U
214 #define IOMUXC_GPIO_SD_09_FLEXIO1_IO15 0x401F8060U, 0x4U, 0, 0, 0x401F8110U
215 #define IOMUXC_GPIO_SD_09_GPIO2_IO09 0x401F8060U, 0x5U, 0, 0, 0x401F8110U
216
217 #define IOMUXC_GPIO_SD_08_FLEXSPI_A_DATA2 0x401F8064U, 0x0U, 0, 0, 0x401F8114U
218 #define IOMUXC_GPIO_SD_08_LPI2C2_SCL 0x401F8064U, 0x1U, 0x401F81C8U, 0x2U, 0x401F8114U
219 #define IOMUXC_GPIO_SD_08_LPSPI1_SCK 0x401F8064U, 0x2U, 0x401F81D4U, 0x1U, 0x401F8114U
220 #define IOMUXC_GPIO_SD_08_FLEXIO1_IO14 0x401F8064U, 0x4U, 0, 0, 0x401F8114U
221 #define IOMUXC_GPIO_SD_08_GPIO2_IO08 0x401F8064U, 0x5U, 0, 0, 0x401F8114U
222
223 #define IOMUXC_GPIO_SD_07_FLEXSPI_A_DATA1 0x401F8068U, 0x0U, 0, 0, 0x401F8118U
224 #define IOMUXC_GPIO_SD_07_LPI2C2_SDA 0x401F8068U, 0x1U, 0x401F81CCU, 0x2U, 0x401F8118U
225 #define IOMUXC_GPIO_SD_07_LPSPI1_PCS0 0x401F8068U, 0x2U, 0x401F81D0U, 0x1U, 0x401F8118U
226 #define IOMUXC_GPIO_SD_07_FLEXIO1_IO13 0x401F8068U, 0x4U, 0, 0, 0x401F8118U
227 #define IOMUXC_GPIO_SD_07_GPIO2_IO07 0x401F8068U, 0x5U, 0, 0, 0x401F8118U
228
229 #define IOMUXC_GPIO_SD_06_FLEXSPI_A_SS0_B 0x401F806CU, 0x0U, 0, 0, 0x401F811CU
230 #define IOMUXC_GPIO_SD_06_LPI2C1_SCL 0x401F806CU, 0x1U, 0x401F81C0U, 0x1U, 0x401F811CU
231 #define IOMUXC_GPIO_SD_06_LPSPI1_SDO 0x401F806CU, 0x2U, 0x401F81DCU, 0x1U, 0x401F811CU
232 #define IOMUXC_GPIO_SD_06_FLEXIO1_IO12 0x401F806CU, 0x4U, 0, 0, 0x401F811CU
233 #define IOMUXC_GPIO_SD_06_GPIO2_IO06 0x401F806CU, 0x5U, 0, 0, 0x401F811CU
234
235 #define IOMUXC_GPIO_SD_05_FLEXSPI_A_SS1_B 0x401F8070U, 0x0U, 0, 0, 0x401F8120U
236 #define IOMUXC_GPIO_SD_05_LPI2C1_SDA 0x401F8070U, 0x1U, 0x401F81C4U, 0x1U, 0x401F8120U
237 #define IOMUXC_GPIO_SD_05_LPSPI1_SDI 0x401F8070U, 0x2U, 0x401F81D8U, 0x1U, 0x401F8120U
238 #define IOMUXC_GPIO_SD_05_FLEXIO1_IO11 0x401F8070U, 0x4U, 0, 0, 0x401F8120U
239 #define IOMUXC_GPIO_SD_05_GPIO2_IO05 0x401F8070U, 0x5U, 0, 0, 0x401F8120U
240
241 #define IOMUXC_GPIO_SD_04_FLEXPWM1_PWM1_A 0x401F8074U, 0x2U, 0x401F8178U, 0x0U, 0x401F8124U
242 #define IOMUXC_GPIO_SD_04_CCM_WAIT 0x401F8074U, 0x3U, 0, 0, 0x401F8124U
243 #define IOMUXC_GPIO_SD_04_FLEXIO1_IO10 0x401F8074U, 0x4U, 0, 0, 0x401F8124U
244 #define IOMUXC_GPIO_SD_04_GPIO2_IO04 0x401F8074U, 0x5U, 0, 0, 0x401F8124U
245 #define IOMUXC_GPIO_SD_04_SRC_BOOT_MODE00 0x401F8074U, 0x6U, 0, 0, 0x401F8124U
246 #define IOMUXC_GPIO_SD_04_FLEXSPI_B_DATA03 0x401F8074U, 0x0U, 0, 0, 0x401F8124U
247 #define IOMUXC_GPIO_SD_04_SAI3_RX_SYNC 0x401F8074U, 0x1U, 0, 0, 0x401F8124U
248
249 #define IOMUXC_GPIO_SD_03_FLEXSPI_B_DATA00 0x401F8078U, 0x0U, 0, 0, 0x401F8128U
250 #define IOMUXC_GPIO_SD_03_SAI3_RX_DATA 0x401F8078U, 0x1U, 0, 0, 0x401F8128U
251 #define IOMUXC_GPIO_SD_03_FLEXPWM1_PWM1_B 0x401F8078U, 0x2U, 0x401F8188U, 0x0U, 0x401F8128U
252 #define IOMUXC_GPIO_SD_03_CCM_REF_EN_B 0x401F8078U, 0x3U, 0, 0, 0x401F8128U
253 #define IOMUXC_GPIO_SD_03_FLEXIO1_IO09 0x401F8078U, 0x4U, 0, 0, 0x401F8128U
254 #define IOMUXC_GPIO_SD_03_GPIO2_IO03 0x401F8078U, 0x5U, 0, 0, 0x401F8128U
255 #define IOMUXC_GPIO_SD_03_SRC_BOOT_MODE01 0x401F8078U, 0x6U, 0, 0, 0x401F8128U
256
257 #define IOMUXC_GPIO_SD_02_FLEXSPI_B_DATA02 0x401F807CU, 0x0U, 0, 0, 0x401F812CU
258 #define IOMUXC_GPIO_SD_02_SAI3_TX_DATA 0x401F807CU, 0x1U, 0, 0, 0x401F812CU
259 #define IOMUXC_GPIO_SD_02_FLEXPWM1_PWM0_A 0x401F807CU, 0x2U, 0x401F8174U, 0x0U, 0x401F812CU
260 #define IOMUXC_GPIO_SD_02_CCM_CLKO1 0x401F807CU, 0x3U, 0, 0, 0x401F812CU
261 #define IOMUXC_GPIO_SD_02_FLEXIO1_IO08 0x401F807CU, 0x4U, 0, 0, 0x401F812CU
262 #define IOMUXC_GPIO_SD_02_GPIO2_IO02 0x401F807CU, 0x5U, 0, 0, 0x401F812CU
263 #define IOMUXC_GPIO_SD_02_SRC_BT_CFG00 0x401F807CU, 0x6U, 0, 0, 0x401F812CU
264
265 #define IOMUXC_GPIO_SD_01_FLEXSPI_B_DATA01 0x401F8080U, 0x0U, 0, 0, 0x401F8130U
266 #define IOMUXC_GPIO_SD_01_SAI3_TX_BCLK 0x401F8080U, 0x1U, 0, 0, 0x401F8130U
267 #define IOMUXC_GPIO_SD_01_FLEXPWM1_PWM0_B 0x401F8080U, 0x2U, 0x401F8184U, 0x0U, 0x401F8130U
268 #define IOMUXC_GPIO_SD_01_CCM_CLKO2 0x401F8080U, 0x3U, 0, 0, 0x401F8130U
269 #define IOMUXC_GPIO_SD_01_FLEXIO1_IO07 0x401F8080U, 0x4U, 0, 0, 0x401F8130U
270 #define IOMUXC_GPIO_SD_01_GPIO2_IO01 0x401F8080U, 0x5U, 0, 0, 0x401F8130U
271 #define IOMUXC_GPIO_SD_01_SRC_BT_CFG01 0x401F8080U, 0x6U, 0, 0, 0x401F8130U
272
273 #define IOMUXC_GPIO_SD_00_FLEXSPI_B_SS0_B 0x401F8084U, 0x0U, 0, 0, 0x401F8134U
274 #define IOMUXC_GPIO_SD_00_SAI3_TX_SYNC 0x401F8084U, 0x1U, 0, 0, 0x401F8134U
275 #define IOMUXC_GPIO_SD_00_ARM_CM7_RXEV 0x401F8084U, 0x2U, 0x401F8220U, 0x1U, 0x401F8134U
276 #define IOMUXC_GPIO_SD_00_CCM_STOP 0x401F8084U, 0x3U, 0, 0, 0x401F8134U
277 #define IOMUXC_GPIO_SD_00_FLEXIO1_IO06 0x401F8084U, 0x4U, 0, 0, 0x401F8134U
278 #define IOMUXC_GPIO_SD_00_GPIO2_IO00 0x401F8084U, 0x5U, 0, 0, 0x401F8134U
279 #define IOMUXC_GPIO_SD_00_SRC_BT_CFG02 0x401F8084U, 0x6U, 0, 0, 0x401F8134U
280
281 #define IOMUXC_GPIO_13_LPUART2_RXD 0x401F8088U, 0x0U, 0x401F81F8U, 0x1U, 0x401F8138U
282 #define IOMUXC_GPIO_13_LPSPI2_PCS2 0x401F8088U, 0x1U, 0, 0, 0x401F8138U
283 #define IOMUXC_GPIO_13_KPP_ROW03 0x401F8088U, 0x2U, 0x401F81B8U, 0x0U, 0x401F8138U
284 #define IOMUXC_GPIO_13_USB_OTG1_ID 0x401F8088U, 0x3U, 0x401F8170U, 0x1U, 0x401F8138U
285 #define IOMUXC_GPIO_13_FLEXIO1_IO05 0x401F8088U, 0x4U, 0, 0, 0x401F8138U
286 #define IOMUXC_GPIO_13_GPIOMUX_IO13 0x401F8088U, 0x5U, 0, 0, 0x401F8138U
287 #define IOMUXC_GPIO_13_SPDIF_LOCK 0x401F8088U, 0x6U, 0, 0, 0x401F8138U
288 #define IOMUXC_GPIO_13_ARM_TRACE1 0x401F8088U, 0x7U, 0, 0, 0x401F8138U
289
290 #define IOMUXC_GPIO_12_LPUART3_TXD 0x401F808CU, 0x0U, 0x401F8204U, 0x1U, 0x401F813CU
291 #define IOMUXC_GPIO_12_LPI2C1_SCL 0x401F808CU, 0x1U, 0x401F81C0U, 0x2U, 0x401F813CU
292 #define IOMUXC_GPIO_12_KPP_COL00 0x401F808CU, 0x2U, 0x401F819CU, 0x1U, 0x401F813CU
293 #define IOMUXC_GPIO_12_USB_OTG1_OC 0x401F808CU, 0x3U, 0x401F821CU, 0x1U, 0x401F813CU
294 #define IOMUXC_GPIO_12_FLEXIO1_IO04 0x401F808CU, 0x4U, 0, 0, 0x401F813CU
295 #define IOMUXC_GPIO_12_GPIOMUX_IO12 0x401F808CU, 0x5U, 0, 0, 0x401F813CU
296 #define IOMUXC_GPIO_12_SPDIF_EXT_CLK 0x401F808CU, 0x6U, 0x401F8218U, 0x0U, 0x401F813CU
297 #define IOMUXC_GPIO_12_ARM_TRACE2 0x401F808CU, 0x7U, 0, 0, 0x401F813CU
298
299 #define IOMUXC_GPIO_11_LPUART3_RXD 0x401F8090U, 0x0U, 0x401F8200U, 0x1U, 0x401F8140U
300 #define IOMUXC_GPIO_11_LPI2C1_SDA 0x401F8090U, 0x1U, 0x401F81C4U, 0x2U, 0x401F8140U
301 #define IOMUXC_GPIO_11_KPP_ROW00 0x401F8090U, 0x2U, 0x401F81ACU, 0x1U, 0x401F8140U
302 #define IOMUXC_GPIO_11_FLEXSPI_B_SS1_B 0x401F8090U, 0x3U, 0, 0, 0x401F8140U
303 #define IOMUXC_GPIO_11_FLEXIO1_IO03 0x401F8090U, 0x4U, 0, 0, 0x401F8140U
304 #define IOMUXC_GPIO_11_GPIOMUX_IO11 0x401F8090U, 0x5U, 0, 0, 0x401F8140U
305 #define IOMUXC_GPIO_11_SPDIF_OUT 0x401F8090U, 0x6U, 0, 0, 0x401F8140U
306 #define IOMUXC_GPIO_11_ARM_TRACE3 0x401F8090U, 0x7U, 0, 0, 0x401F8140U
307
308 #define IOMUXC_GPIO_10_LPUART1_TXD 0x401F8094U, 0x0U, 0x401F81F4U, 0x1U, 0x401F8144U
309 #define IOMUXC_GPIO_10_LPI2C1_HREQ 0x401F8094U, 0x1U, 0x401F81BCU, 0x1U, 0x401F8144U
310 #define IOMUXC_GPIO_10_EWM_OUT_B 0x401F8094U, 0x2U, 0, 0, 0x401F8144U
311 #define IOMUXC_GPIO_10_LPI2C2_SCL 0x401F8094U, 0x3U, 0x401F81C8U, 0x3U, 0x401F8144U
312 #define IOMUXC_GPIO_10_FLEXIO1_IO02 0x401F8094U, 0x4U, 0, 0, 0x401F8144U
313 #define IOMUXC_GPIO_10_GPIOMUX_IO10 0x401F8094U, 0x5U, 0, 0, 0x401F8144U
314 #define IOMUXC_GPIO_10_SPDIF_IN 0x401F8094U, 0x6U, 0x401F8214U, 0x0U, 0x401F8144U
315
316 #define IOMUXC_GPIO_09_LPUART1_RXD 0x401F8098U, 0x0U, 0x401F81F0U, 0x1U, 0x401F8148U
317 #define IOMUXC_GPIO_09_WDOG1_B 0x401F8098U, 0x1U, 0, 0, 0x401F8148U
318 #define IOMUXC_GPIO_09_FLEXSPI_A_SS1_B 0x401F8098U, 0x2U, 0, 0, 0x401F8148U
319 #define IOMUXC_GPIO_09_LPI2C2_SDA 0x401F8098U, 0x3U, 0x401F81CCU, 0x3U, 0x401F8148U
320 #define IOMUXC_GPIO_09_FLEXIO1_IO01 0x401F8098U, 0x4U, 0, 0, 0x401F8148U
321 #define IOMUXC_GPIO_09_GPIOMUX_IO09 0x401F8098U, 0x5U, 0, 0, 0x401F8148U
322 #define IOMUXC_GPIO_09_SPDIF_SR_CLK 0x401F8098U, 0x6U, 0, 0, 0x401F8148U
323
324 #define IOMUXC_GPIO_08_SAI1_MCLK 0x401F809CU, 0x0U, 0, 0, 0x401F814CU
325 #define IOMUXC_GPIO_08_GPT1_CLK 0x401F809CU, 0x1U, 0, 0, 0x401F814CU
326 #define IOMUXC_GPIO_08_FLEXPWM1_PWM3_A 0x401F809CU, 0x2U, 0x401F8180U, 0x1U, 0x401F814CU
327 #define IOMUXC_GPIO_08_LPUART3_TXD 0x401F809CU, 0x3U, 0x401F8204U, 0x2U, 0x401F814CU
328 #define IOMUXC_GPIO_08_FLEXIO1_IO00 0x401F809CU, 0x4U, 0, 0, 0x401F814CU
329 #define IOMUXC_GPIO_08_GPIOMUX_IO08 0x401F809CU, 0x5U, 0, 0, 0x401F814CU
330 #define IOMUXC_GPIO_08_LPUART1_CTS_B 0x401F809CU, 0x6U, 0, 0, 0x401F814CU
331
332 #define IOMUXC_GPIO_07_SAI1_TX_SYNC 0x401F80A0U, 0x0U, 0, 0, 0x401F8150U
333 #define IOMUXC_GPIO_07_GPT1_COMPARE1 0x401F80A0U, 0x1U, 0, 0, 0x401F8150U
334 #define IOMUXC_GPIO_07_FLEXPWM1_PWM3_B 0x401F80A0U, 0x2U, 0x401F8190U, 0x1U, 0x401F8150U
335 #define IOMUXC_GPIO_07_LPUART3_RXD 0x401F80A0U, 0x3U, 0x401F8200U, 0x2U, 0x401F8150U
336 #define IOMUXC_GPIO_07_SPDIF_LOCK 0x401F80A0U, 0x4U, 0, 0, 0x401F8150U
337 #define IOMUXC_GPIO_07_GPIOMUX_IO07 0x401F80A0U, 0x5U, 0, 0, 0x401F8150U
338 #define IOMUXC_GPIO_07_LPUART1_RTS_B 0x401F80A0U, 0x6U, 0, 0, 0x401F8150U
339
340 #define IOMUXC_GPIO_06_SAI1_TX_BCLK 0x401F80A4U, 0x0U, 0, 0, 0x401F8154U
341 #define IOMUXC_GPIO_06_GPT1_CAPTURE1 0x401F80A4U, 0x1U, 0, 0, 0x401F8154U
342 #define IOMUXC_GPIO_06_FLEXPWM1_PWM2_A 0x401F80A4U, 0x2U, 0x401F817CU, 0x1U, 0x401F8154U
343 #define IOMUXC_GPIO_06_LPUART4_TXD 0x401F80A4U, 0x3U, 0x401F820CU, 0x1U, 0x401F8154U
344 #define IOMUXC_GPIO_06_SPDIF_EXT_CLK 0x401F80A4U, 0x4U, 0x401F8218U, 0x1U, 0x401F8154U
345 #define IOMUXC_GPIO_06_GPIOMUX_IO06 0x401F80A4U, 0x5U, 0, 0, 0x401F8154U
346
347 #define IOMUXC_GPIO_05_SAI1_TX_DATA01 0x401F80A8U, 0x0U, 0, 0, 0x401F8158U
348 #define IOMUXC_GPIO_05_GPT1_COMPARE2 0x401F80A8U, 0x1U, 0, 0, 0x401F8158U
349 #define IOMUXC_GPIO_05_FLEXPWM1_PWM2_B 0x401F80A8U, 0x2U, 0x401F818CU, 0x1U, 0x401F8158U
350 #define IOMUXC_GPIO_05_LPUART4_RXD 0x401F80A8U, 0x3U, 0x401F8208U, 0x1U, 0x401F8158U
351 #define IOMUXC_GPIO_05_SPDIF_OUT 0x401F80A8U, 0x4U, 0, 0, 0x401F8158U
352 #define IOMUXC_GPIO_05_GPIOMUX_IO05 0x401F80A8U, 0x5U, 0, 0, 0x401F8158U
353
354 #define IOMUXC_GPIO_04_SAI1_TX_DATA00 0x401F80ACU, 0x0U, 0, 0, 0x401F815CU
355 #define IOMUXC_GPIO_04_GPT1_CAPTURE2 0x401F80ACU, 0x1U, 0, 0, 0x401F815CU
356 #define IOMUXC_GPIO_04_FLEXPWM1_PWM1_A 0x401F80ACU, 0x2U, 0x401F8178U, 0x1U, 0x401F815CU
357 #define IOMUXC_GPIO_04_SPDIF_IN 0x401F80ACU, 0x4U, 0x401F8214U, 0x1U, 0x401F815CU
358 #define IOMUXC_GPIO_04_GPIOMUX_IO04 0x401F80ACU, 0x5U, 0, 0, 0x401F815CU
359
360 #define IOMUXC_GPIO_03_SAI1_RX_DATA00 0x401F80B0U, 0x0U, 0, 0, 0x401F8160U
361 #define IOMUXC_GPIO_03_GPT1_COMPARE3 0x401F80B0U, 0x1U, 0, 0, 0x401F8160U
362 #define IOMUXC_GPIO_03_FLEXPWM1_PWM1_B 0x401F80B0U, 0x2U, 0x401F8188U, 0x1U, 0x401F8160U
363 #define IOMUXC_GPIO_03_SPDIF_SR_CLK 0x401F80B0U, 0x4U, 0, 0, 0x401F8160U
364 #define IOMUXC_GPIO_03_GPIOMUX_IO03 0x401F80B0U, 0x5U, 0, 0, 0x401F8160U
365
366 #define IOMUXC_GPIO_02_SAI1_RX_SYNC 0x401F80B4U, 0x0U, 0, 0, 0x401F8164U
367 #define IOMUXC_GPIO_02_WDOG2_B 0x401F80B4U, 0x1U, 0, 0, 0x401F8164U
368 #define IOMUXC_GPIO_02_FLEXPWM1_PWM0_A 0x401F80B4U, 0x2U, 0x401F8174U, 0x1U, 0x401F8164U
369 #define IOMUXC_GPIO_02_LPI2C1_SCL 0x401F80B4U, 0x3U, 0x401F81C0U, 0x3U, 0x401F8164U
370 #define IOMUXC_GPIO_02_KPP_COL03 0x401F80B4U, 0x4U, 0x401F81A8U, 0x1U, 0x401F8164U
371 #define IOMUXC_GPIO_02_GPIOMUX_IO02 0x401F80B4U, 0x5U, 0, 0, 0x401F8164U
372
373 #define IOMUXC_GPIO_01_SAI1_RX_BCLK 0x401F80B8U, 0x0U, 0, 0, 0x401F8168U
374 #define IOMUXC_GPIO_01_WDOG1_ANY 0x401F80B8U, 0x1U, 0, 0, 0x401F8168U
375 #define IOMUXC_GPIO_01_FLEXPWM1_PWM0_B 0x401F80B8U, 0x2U, 0x401F8184U, 0x1U, 0x401F8168U
376 #define IOMUXC_GPIO_01_LPI2C1_SDA 0x401F80B8U, 0x3U, 0x401F81C4U, 0x3U, 0x401F8168U
377 #define IOMUXC_GPIO_01_KPP_ROW03 0x401F80B8U, 0x4U, 0x401F81B8U, 0x1U, 0x401F8168U
378 #define IOMUXC_GPIO_01_GPIOMUX_IO01 0x401F80B8U, 0x5U, 0, 0, 0x401F8168U
379
380 #define IOMUXC_GPIO_00_FLEXSPI_B_DQS 0x401F80BCU, 0x0U, 0x401F8198U, 0x1U, 0x401F816CU
381 #define IOMUXC_GPIO_00_SAI3_MCLK 0x401F80BCU, 0x1U, 0, 0, 0x401F816CU
382 #define IOMUXC_GPIO_00_LPSPI2_PCS3 0x401F80BCU, 0x2U, 0, 0, 0x401F816CU
383 #define IOMUXC_GPIO_00_LPSPI1_PCS3 0x401F80BCU, 0x3U, 0, 0, 0x401F816CU
384 #define IOMUXC_GPIO_00_PIT_TRIGGER00 0x401F80BCU, 0x4U, 0, 0, 0x401F816CU
385 #define IOMUXC_GPIO_00_GPIOMUX_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F816CU
386
387 /*@}*/
388
389 #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
390 #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U)
391
392 typedef enum _iomuxc_gpr_mode
393 {
394 kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK,
395 kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK,
396 kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK,
397 kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK,
398 kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK,
399 } iomuxc_gpr_mode_t;
400
401 typedef enum _iomuxc_gpr_saimclk
402 {
403 kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT,
404 kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT,
405 kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT,
406 kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT,
407 } iomuxc_gpr_saimclk_t;
408
409 typedef enum _iomuxc_mqs_pwm_oversample_rate
410 {
411 kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */
412 kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */
413 } iomuxc_mqs_pwm_oversample_rate_t;
414
415 #if defined(__cplusplus)
416 extern "C" {
417 #endif /*_cplusplus */
418
419 /*! @name Configuration */
420 /*@{*/
421
422 /*!
423 * @brief Sets the IOMUXC pin mux mode.
424 * @note The first five parameters can be filled with the pin function ID macros.
425 *
426 * This is an example to set the PTA6 as the lpuart0_tx:
427 * @code
428 * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0);
429 * @endcode
430 *
431 * This is an example to set the PTA0 as GPIOA0:
432 * @code
433 * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0);
434 * @endcode
435 *
436 * @param muxRegister The pin mux register.
437 * @param muxMode The pin mux mode.
438 * @param inputRegister The select input register.
439 * @param inputDaisy The input daisy.
440 * @param configRegister The config register.
441 * @param inputOnfield Software input on field.
442 */
IOMUXC_SetPinMux(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t inputOnfield)443 static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
444 uint32_t muxMode,
445 uint32_t inputRegister,
446 uint32_t inputDaisy,
447 uint32_t configRegister,
448 uint32_t inputOnfield)
449 {
450 *((volatile uint32_t *)muxRegister) =
451 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
452
453 if (inputRegister != 0UL)
454 {
455 *((volatile uint32_t *)inputRegister) = inputDaisy;
456 }
457 }
458
459 /*!
460 * @brief Sets the IOMUXC pin configuration.
461 * @note The previous five parameters can be filled with the pin function ID macros.
462 *
463 * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS:
464 * @code
465 * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U))
466 * @endcode
467 *
468 * @param muxRegister The pin mux register.
469 * @param muxMode The pin mux mode.
470 * @param inputRegister The select input register.
471 * @param inputDaisy The input daisy.
472 * @param configRegister The config register.
473 * @param configValue The pin config value.
474 */
IOMUXC_SetPinConfig(uint32_t muxRegister,uint32_t muxMode,uint32_t inputRegister,uint32_t inputDaisy,uint32_t configRegister,uint32_t configValue)475 static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
476 uint32_t muxMode,
477 uint32_t inputRegister,
478 uint32_t inputDaisy,
479 uint32_t configRegister,
480 uint32_t configValue)
481 {
482 if (configRegister != 0UL)
483 {
484 *((volatile uint32_t *)configRegister) = configValue;
485 }
486 }
487
488 /*!
489 * @brief Sets IOMUXC general configuration for some mode.
490 *
491 * @param base The IOMUXC GPR base address.
492 * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode"
493 * @param enable True enable false disable.
494 */
IOMUXC_EnableMode(IOMUXC_GPR_Type * base,uint32_t mode,bool enable)495 static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
496 {
497 mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK |
498 IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
499
500 if (enable)
501 {
502 base->GPR1 |= mode;
503 }
504 else
505 {
506 base->GPR1 &= ~mode;
507 }
508 }
509
510 /*!
511 * @brief Sets IOMUXC general configuration for SAI MCLK selection.
512 *
513 * @param base The IOMUXC GPR base address.
514 * @param mclk The SAI MCLK.
515 * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM.
516 */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type * base,iomuxc_gpr_saimclk_t mclk,uint8_t clkSrc)517 static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc)
518 {
519 uint32_t gpr;
520
521 if (mclk > kIOMUXC_GPR_SAI1MClk2Sel)
522 {
523 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk);
524 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr;
525 }
526 else
527 {
528 gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk);
529 base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr;
530 }
531 }
532
533 /*!
534 * @brief Enters or exit MQS software reset.
535 *
536 * @param base The IOMUXC GPR base address.
537 * @param enable Enter or exit MQS software reset.
538 */
IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type * base,bool enable)539 static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable)
540 {
541 if (enable)
542 {
543 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
544 }
545 else
546 {
547 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK;
548 }
549 }
550
551 /*!
552 * @brief Enables or disables MQS.
553 *
554 * @param base The IOMUXC GPR base address.
555 * @param enable Enable or disable the MQS.
556 */
IOMUXC_MQSEnable(IOMUXC_GPR_Type * base,bool enable)557 static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable)
558 {
559 if (enable)
560 {
561 base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK;
562 }
563 else
564 {
565 base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK;
566 }
567 }
568
569 /*!
570 * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk.
571 *
572 * @param base The IOMUXC GPR base address.
573 * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t".
574 * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq.
575 */
576
IOMUXC_MQSConfig(IOMUXC_GPR_Type * base,iomuxc_mqs_pwm_oversample_rate_t rate,uint8_t divider)577 static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider)
578 {
579 uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK);
580 base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider);
581 }
582
583 /*@}*/
584
585 #if defined(__cplusplus)
586 }
587 #endif /*_cplusplus */
588
589 /*! @}*/
590
591 #endif /* _FSL_IOMUXC_H_ */
592
