1 /*
2 * Copyright 2017-2021 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_FLEXRAM_H_
10 #define _FSL_FLEXRAM_H_
11
12 #include "fsl_common.h"
13 #include "fsl_flexram_allocate.h"
14
15 /*!
16 * @addtogroup flexram
17 * @{
18 */
19
20 /******************************************************************************
21 * Definitions.
22 *****************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 /*! @brief Driver version 2.1.0. */
27 #define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U))
28 /*@}*/
29
30 /*! @brief Get ECC error detailed information. */
31 #ifndef FLEXRAM_ECC_ERROR_DETAILED_INFO
32 #define FLEXRAM_ECC_ERROR_DETAILED_INFO \
33 0U /* Define to zero means get raw ECC error information, which needs parse it by user. */
34 #endif
35
36 /*! @brief Flexram write/read selection. */
37 enum
38 {
39 kFLEXRAM_Read = 0U, /*!< read */
40 kFLEXRAM_Write = 1U, /*!< write */
41 };
42
43 /*! @brief Interrupt status flag mask */
44 enum
45 {
46 kFLEXRAM_OCRAMAccessError = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK, /*!< OCRAM accesses unallocated address */
47 kFLEXRAM_DTCMAccessError = FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK, /*!< DTCM accesses unallocated address */
48 kFLEXRAM_ITCMAccessError = FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< ITCM accesses unallocated address */
49
50 #if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
51 kFLEXRAM_OCRAMMagicAddrMatch = FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK, /*!< OCRAM magic address match */
52 kFLEXRAM_DTCMMagicAddrMatch = FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK, /*!< DTCM magic address match */
53 kFLEXRAM_ITCMMagicAddrMatch = FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK, /*!< ITCM magic address match */
54
55 #if defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC
56 kFLEXRAM_OCRAMECCMultiError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK,
57 kFLEXRAM_OCRAMECCSingleError = FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK,
58 kFLEXRAM_ITCMECCMultiError = FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK,
59 kFLEXRAM_ITCMECCSingleError = FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK,
60 kFLEXRAM_D0TCMECCMultiError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK,
61 kFLEXRAM_D0TCMECCSingleError = FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK,
62 kFLEXRAM_D1TCMECCMultiError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK,
63 kFLEXRAM_D1TCMECCSingleError = FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
64
65 kFLEXRAM_InterruptStatusAll =
66 FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
67 FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
68 FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK |
69 FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK |
70 FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK |
71 FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK |
72 FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK | FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK,
73 #else
74 kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
75 FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK |
76 FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK | FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK,
77 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
78
79 /*!< all the interrupt status mask */
80 #else
81 kFLEXRAM_InterruptStatusAll = FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK | FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK |
82 FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK, /*!< all the interrupt status mask */
83 #endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
84
85 };
86
87 /*! @brief FLEXRAM TCM access mode.
88 * Fast access mode expected to be finished in 1-cycle;
89 * Wait access mode expected to be finished in 2-cycle.
90 * Wait access mode is a feature of the flexram and it should be used when
91 * the CPU clock is too fast to finish TCM access in 1-cycle.
92 * Normally, fast mode is the default mode, the efficiency of the TCM access will better.
93 */
94 typedef enum _flexram_tcm_access_mode
95 {
96 kFLEXRAM_TCMAccessFastMode = 0U, /*!< fast access mode */
97 kFLEXRAM_TCMAccessWaitMode = 1U, /*!< wait access mode */
98 } flexram_tcm_access_mode_t;
99
100 /*! @brief FLEXRAM TCM support size */
101 enum
102 {
103 kFLEXRAM_TCMSize32KB = 32 * 1024U, /*!< TCM total size be 32KB */
104 kFLEXRAM_TCMSize64KB = 64 * 1024U, /*!< TCM total size be 64KB */
105 kFLEXRAM_TCMSize128KB = 128 * 1024U, /*!< TCM total size be 128KB */
106 kFLEXRAM_TCMSize256KB = 256 * 1024U, /*!< TCM total size be 256KB */
107 kFLEXRAM_TCMSize512KB = 512 * 1024U, /*!< TCM total size be 512KB */
108 };
109
110 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
111 /*! @brief FLEXRAM ocram ecc single error information, including single error information, error address, error data */
112 typedef struct _flexram_ocram_ecc_single_error_info
113 {
114 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
115 uint8_t OcramSingleErrorECCCipher; /*!< OCRAM corresponding ECC cipher of OCRAM single-bit ECC error. */
116 uint8_t OcramSingleErrorECCSyndrome; /*!< OCRAM corresponding ECC syndrome of OCRAM single-bit ECC error,
117 which can be used to locate the Error bit using a look-up table. */
118 #else
119 uint32_t OcramSingleErrorInfo; /*!< Ocram single error information, user should parse it by themself. */
120 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
121 uint32_t OcramSingleErrorAddr; /*!< Ocram single error address */
122 uint32_t OcramSingleErrorDataLSB; /*!< Ocram single error data LSB */
123 uint32_t OcramSingleErrorDataMSB; /*!< Ocram single error data MSB */
124 } flexram_ocram_ecc_single_error_info_t;
125
126 /*! @brief FLEXRAM ocram ecc multiple error information, including multiple error information, error address, error data
127 */
128 typedef struct _flexram_ocram_ecc_multi_error_info
129 {
130 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
131 uint8_t OcramMultiErrorECCCipher; /*!< OCRAM corresponding ECC cipher of OCRAM multi-bit ECC error. */
132 #else
133 uint32_t OcramMultiErrorInfo; /*!< Ocram single error information, user should parse it by themself. */
134 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
135 uint32_t OcramMultiErrorAddr; /*!< Ocram multiple error address */
136 uint32_t OcramMultiErrorDataLSB; /*!< Ocram multiple error data LSB */
137 uint32_t OcramMultiErrorDataMSB; /*!< Ocram multiple error data MSB */
138 } flexram_ocram_ecc_multi_error_info_t;
139
140 /*! @brief FLEXRAM itcm ecc single error information, including single error information, error address, error data */
141 typedef struct _flexram_itcm_ecc_single_error_info
142 {
143 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
144 uint8_t ItcmSingleErrorTCMWriteRead; /*!< itcm single-bit ECC error corresponding tcm_wr value, which is to tell
145 whether it is a write access(0x01) or a read access(0x00). */
146 uint8_t ItcmSingleErrorTCMAccessSize; /*!< itcm single-bit ECC error corresponding tcm access size,
147 which should be 3 (64bit). */
148 uint8_t ItcmSingleErrorTCMMaster; /*!< itcm single-bit ECC error corresponding tcm_master,
149 which is to tell the requester of the current access. */
150 uint8_t ItcmSingleErrorTCMPrivilege; /*!< itcm single-bit ECC error corresponding tcm_priv,
151 which is to tell the privilege level of access. */
152 uint8_t ItcmSingleErrorBitPostion; /*!< itcm single-bit ECC error corresponding bit postion. */
153 #else
154 uint32_t ItcmSingleErrorInfo; /*!< itcm single error information, user should parse it by themself. */
155 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
156 uint32_t ItcmSingleErrorAddr; /*!< itcm single error address */
157 uint32_t ItcmSingleErrorDataLSB; /*!< itcm single error data LSB */
158 uint32_t ItcmSingleErrorDataMSB; /*!< itcm single error data MSB */
159 } flexram_itcm_ecc_single_error_info_t;
160
161 /*! @brief FLEXRAM itcm ecc multiple error information, including multiple error information, error address, error data
162 */
163 typedef struct _flexram_itcm_ecc_multi_error_info
164 {
165 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
166 uint8_t ItcmMultiErrorTCMWriteRead; /*!< itcm multiple-bit ECC error corresponding tcm_wr value, which is to tell
167 whether it is a write access(0x01) or a read access(0x00). */
168 uint8_t ItcmMultiErrorTCMAccessSize; /*!< itcm multiple-bit ECC error corresponding tcm access size,
169 which should be 3 (64bit). */
170 uint8_t ItcmMultiErrorTCMMaster; /*!< itcm multiple-bit ECC error corresponding tcm_master,
171 which is to tell the requester of the current access. */
172 uint8_t ItcmMultiErrorTCMPrivilege; /*!< itcm multiple-bit ECC error corresponding tcm_priv,
173 which is to tell the privilege level of access. */
174 uint8_t ItcmMultiErrorECCSyndrome; /*!< itcm multiple-bit ECC error corresponding syndrome,
175 which can not be used to locate the Error bit using a look-up table. */
176 #else
177 uint32_t ItcmMultiErrorInfo; /*!< itcm multiple error information, user should parse it by themself. */
178 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
179 uint32_t ItcmMultiErrorAddr; /*!< itcm multiple error address */
180 uint32_t ItcmMultiErrorDataLSB; /*!< itcm multiple error data LSB */
181 uint32_t ItcmMultiErrorDataMSB; /*!< itcm multiple error data MSB */
182 } flexram_itcm_ecc_multi_error_info_t;
183
184 /*! @brief FLEXRAM dtcm ecc single error information, including single error information, error address, error data */
185 typedef struct _flexram_dtcm_ecc_single_error_info
186 {
187 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
188 uint8_t DtcmSingleErrorTCMWriteRead; /*!< dtcm single-bit ECC error corresponding tcm_wr value, which is to tell
189 whether it is a write access(0x01) or a read access(0x00). */
190 uint8_t DtcmSingleErrorTCMAccessSize; /*!< dtcm single-bit ECC error corresponding tcm access size,
191 which should be 2 (32bit). */
192 uint8_t DtcmSingleErrorTCMMaster; /*!< dtcm single-bit ECC error corresponding tcm_master,
193 which is to tell the requester of the current access. */
194 uint8_t DtcmSingleErrorTCMPrivilege; /*!< dtcm single-bit ECC error corresponding tcm_priv,
195 which is to tell the privilege level of access. */
196 uint8_t DtcmSingleErrorBitPostion; /*!< dtcm single-bit ECC error corresponding bit postion. */
197 #else
198 uint32_t DtcmSingleErrorInfo; /*!< dtcm single error information, user should parse it by themself. */
199 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
200 uint32_t DtcmSingleErrorAddr; /*!< dtcm single error address */
201 uint32_t DtcmSingleErrorData; /*!< dtcm single error data */
202 } flexram_dtcm_ecc_single_error_info_t;
203
204 /*! @brief FLEXRAM dtcm ecc multiple error information, including multiple error information, error address, error data
205 */
206 typedef struct _flexram_dtcm_ecc_multi_error_info
207 {
208 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
209 uint8_t DtcmMultiErrorTCMWriteRead; /*!< dtcm multiple-bit ECC error corresponding tcm_wr value, which is to tell
210 whether it is a write access(0x01) or a read access(0x00). */
211 uint8_t DtcmMultiErrorTCMAccessSize; /*!< dtcm multiple-bit ECC error corresponding tcm access size,
212 which should be 3 (64bit). */
213 uint8_t DtcmMultiErrorTCMMaster; /*!< dtcm multiple-bit ECC error corresponding tcm_master,
214 which is to tell the requester of the current access. */
215 uint8_t DtcmMultiErrorTCMPrivilege; /*!< dtcm multiple-bit ECC error corresponding tcm_priv,
216 which is to tell the privilege level of access. */
217 uint8_t DtcmMultiErrorECCSyndrome; /*!< dtcm multiple-bit ECC error corresponding syndrome,
218 which can not be used to locate the Error bit using a look-up table. */
219 #else
220 uint32_t DtcmMultiErrorInfo; /*!< dtcm multiple error information, user should parse it by themself. */
221 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
222 uint32_t DtcmMultiErrorAddr; /*!< dtcm multiple error address */
223 uint32_t DtcmMultiErrorData; /*!< dtcm multiple error data */
224 } flexram_dtcm_ecc_multi_error_info_t;
225
226 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
227
228 /*******************************************************************************
229 * APIs
230 ******************************************************************************/
231
232 #if defined(__cplusplus)
233 extern "C" {
234 #endif
235
236 /*!
237 * @name Initialization and de-initialization
238 * @{
239 */
240
241 /*!
242 * @brief FLEXRAM module initialization function.
243 *
244 * @param base FLEXRAM base address.
245 */
246 void FLEXRAM_Init(FLEXRAM_Type *base);
247
248 /*!
249 * @brief De-initializes the FLEXRAM.
250 *
251 */
252 void FLEXRAM_Deinit(FLEXRAM_Type *base);
253
254 /* @} */
255
256 /*!
257 * @name Status
258 * @{
259 */
260 /*!
261 * @brief FLEXRAM module gets interrupt status.
262 *
263 * @param base FLEXRAM base address.
264 */
FLEXRAM_GetInterruptStatus(FLEXRAM_Type * base)265 static inline uint32_t FLEXRAM_GetInterruptStatus(FLEXRAM_Type *base)
266 {
267 return base->INT_STATUS & (uint32_t)kFLEXRAM_InterruptStatusAll;
268 }
269
270 /*!
271 * @brief FLEXRAM module clears interrupt status.
272 *
273 * @param base FLEXRAM base address.
274 * @param status Status to be cleared.
275 */
FLEXRAM_ClearInterruptStatus(FLEXRAM_Type * base,uint32_t status)276 static inline void FLEXRAM_ClearInterruptStatus(FLEXRAM_Type *base, uint32_t status)
277 {
278 base->INT_STATUS |= status;
279 }
280
281 /*!
282 * @brief FLEXRAM module enables interrupt status.
283 *
284 * @param base FLEXRAM base address.
285 * @param status Status to be enabled.
286 */
FLEXRAM_EnableInterruptStatus(FLEXRAM_Type * base,uint32_t status)287 static inline void FLEXRAM_EnableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
288 {
289 base->INT_STAT_EN |= status;
290 }
291
292 /*!
293 * @brief FLEXRAM module disable interrupt status.
294 *
295 * @param base FLEXRAM base address.
296 * @param status Status to be disabled.
297 */
FLEXRAM_DisableInterruptStatus(FLEXRAM_Type * base,uint32_t status)298 static inline void FLEXRAM_DisableInterruptStatus(FLEXRAM_Type *base, uint32_t status)
299 {
300 base->INT_STAT_EN &= ~status;
301 }
302
303 /* @} */
304
305 /*!
306 * @name Interrupts
307 * @{
308 */
309
310 /*!
311 * @brief FLEXRAM module enables interrupt.
312 *
313 * @param base FLEXRAM base address.
314 * @param status Status interrupt to be enabled.
315 */
FLEXRAM_EnableInterruptSignal(FLEXRAM_Type * base,uint32_t status)316 static inline void FLEXRAM_EnableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
317 {
318 base->INT_SIG_EN |= status;
319 }
320
321 /*!
322 * @brief FLEXRAM module disables interrupt.
323 *
324 * @param base FLEXRAM base address.
325 * @param status Status interrupt to be disabled.
326 */
FLEXRAM_DisableInterruptSignal(FLEXRAM_Type * base,uint32_t status)327 static inline void FLEXRAM_DisableInterruptSignal(FLEXRAM_Type *base, uint32_t status)
328 {
329 base->INT_SIG_EN &= ~status;
330 }
331 /* @} */
332
333 /*!
334 * @brief FLEXRAM module sets TCM read access mode
335 *
336 * @param base FLEXRAM base address.
337 * @param mode Access mode.
338 */
FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type * base,flexram_tcm_access_mode_t mode)339 static inline void FLEXRAM_SetTCMReadAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
340 {
341 base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK;
342 base->TCM_CTRL |= (uint32_t)mode;
343 }
344
345 /*!
346 * @brief FLEXRAM module set TCM write access mode
347 *
348 * @param base FLEXRAM base address.
349 * @param mode Access mode.
350 */
FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type * base,flexram_tcm_access_mode_t mode)351 static inline void FLEXRAM_SetTCMWriteAccessMode(FLEXRAM_Type *base, flexram_tcm_access_mode_t mode)
352 {
353 base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK;
354 base->TCM_CTRL |= (uint32_t)mode;
355 }
356
357 /*!
358 * @brief FLEXRAM module force ram clock on
359 *
360 * @param base FLEXRAM base address.
361 * @param enable Enable or disable clock force on.
362 */
FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type * base,bool enable)363 static inline void FLEXRAM_EnableForceRamClockOn(FLEXRAM_Type *base, bool enable)
364 {
365 if (enable)
366 {
367 base->TCM_CTRL |= FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
368 }
369 else
370 {
371 base->TCM_CTRL &= ~FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK;
372 }
373 }
374
375 #if defined(FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR) && FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR
376 /*!
377 * @brief FLEXRAM OCRAM magic addr configuration.
378 * When read/write access hit magic address, it will generate interrupt.
379 * @param base FLEXRAM base address.
380 * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
381 * @param rwSel Read/write selection. 0 for read access while 1 for write access.
382 */
FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type * base,uint16_t magicAddr,uint32_t rwSel)383 static inline void FLEXRAM_SetOCRAMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
384 {
385 base->OCRAM_MAGIC_ADDR = FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(rwSel) |
386 FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
387 }
388
389 /*!
390 * @brief FLEXRAM DTCM magic addr configuration.
391 * When read/write access hits magic address, it will generate interrupt.
392 * @param base FLEXRAM base address.
393 * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
394 * @param rwSel Read/write selection. 0 for read access while 1 write access.
395 */
FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type * base,uint16_t magicAddr,uint32_t rwSel)396 static inline void FLEXRAM_SetDTCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
397 {
398 base->DTCM_MAGIC_ADDR = FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(rwSel) |
399 FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
400 }
401
402 /*!
403 * @brief FLEXRAM ITCM magic addr configuration.
404 * When read/write access hits magic address, it will generate interrupt.
405 * @param base FLEXRAM base address.
406 * @param magicAddr Magic address, the actual address bits [18:3] is corresponding to the register field [16:1].
407 * @param rwSel Read/write selection. 0 for read access while 1 for write access.
408 */
FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type * base,uint16_t magicAddr,uint32_t rwSel)409 static inline void FLEXRAM_SetITCMMagicAddr(FLEXRAM_Type *base, uint16_t magicAddr, uint32_t rwSel)
410 {
411 base->ITCM_MAGIC_ADDR = FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(rwSel) |
412 FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR((uint32_t)magicAddr >> 3);
413 }
414 #endif /* FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR */
415
416 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
417 /*!
418 * @brief FLEXRAM get ocram ecc single error information.
419 * @param base FLEXRAM base address.
420 * @param OcramECCEnable ocram ecc enablement.
421 * @param TcmECCEnable tcm(itcm/d0tcm/d1tcm) ecc enablement.
422 */
423 void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable);
424
425 /*!
426 * @brief FLEXRAM get ocram ecc single error information.
427 * @param base FLEXRAM base address.
428 * @param info ecc error information.
429 */
430 void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info);
431
432 /*!
433 * @brief FLEXRAM get ocram ecc multiple error information.
434 * @param base FLEXRAM base address.
435 * @param info ecc error information.
436 */
437 void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info);
438
439 /*!
440 * @brief FLEXRAM get itcm ecc single error information.
441 * @param base FLEXRAM base address.
442 * @param info ecc error information.
443 */
444 void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info);
445
446 /*!
447 * @brief FLEXRAM get itcm ecc multiple error information.
448 * @param base FLEXRAM base address.
449 * @param info ecc error information.
450 */
451 void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info);
452
453 /*!
454 * @brief FLEXRAM get d0tcm ecc single error information.
455 * @param base FLEXRAM base address.
456 * @param info ecc error information.
457 * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM.
458 */
459 void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank);
460
461 /*!
462 * @brief FLEXRAM get d0tcm ecc multiple error information.
463 * @param base FLEXRAM base address.
464 * @param info ecc error information.
465 * @param bank DTCM bank, 0 is D0TCM, 1 is D1TCM.
466 */
467 void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank);
468
469 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
470
471 #if defined(__cplusplus)
472 }
473 #endif
474
475 /*! @}*/
476
477 #endif
478
