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Searched refs:FIFOWR (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-2.7.6/mcux/drivers/imxrt6xx/
Dfsl_i2s.c820 base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); in I2S_TxHandleIRQ()
830 base->FIFOWR = (data & 0xFFU); in I2S_TxHandleIRQ()
837 base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); in I2S_TxHandleIRQ()
848 base->FIFOWR = data & 0xFFFFU; in I2S_TxHandleIRQ()
855 base->FIFOWR = data; in I2S_TxHandleIRQ()
875 base->FIFOWR = *((volatile uint32_t *)(dataAddr)); in I2S_TxHandleIRQ()
894 base->FIFOWR = data; in I2S_TxHandleIRQ()
903 base->FIFOWR = *((volatile uint32_t *)(dataAddr)); in I2S_TxHandleIRQ()
948 base->FIFOWR = 0U; in I2S_TxHandleIRQ()
954 base->FIFOWR = 0U; in I2S_TxHandleIRQ()
Dfsl_i2s_dma.c297 base->FIFOWR = 0U; in I2S_TransferAbortDMA()
457 destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); in I2S_StartTransferDMA()
502 …((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_Dummy… in I2S_StartTransferDMA()
552 destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); in I2S_AddTransferDMA()
Dfsl_spi_dma.c278 address = (uint32_t)&base->FIFOWR; in SPI_MasterTransferDMA()
392 *((uint16_t *)((uint32_t)&base->FIFOWR) + 1) = (uint16_t)(tmpData >> 16U); in SPI_MasterTransferDMA()
398 *((uint16_t *)((uint32_t)&base->FIFOWR) + 1) = (uint16_t)(tmpData >> 16U); in SPI_MasterTransferDMA()
Dfsl_usart.c492 base->FIFOWR = ((uint32_t)address | 0x100UL); in USART_SendAddress()
541 base->FIFOWR = *data; in USART_WriteBlocking()
1115 base->FIFOWR = *handle->txData; in USART_TransferHandleIRQ()
Dfsl_spi.c453 base->FIFOWR = data | control; in SPI_WriteData()
624 base->FIFOWR = tmp32; in SPI_MasterTransferBlocking()
980 base->FIFOWR = tmp32; in SPI_TransferHandleIRQInternal()
Dfsl_usart_dma.c203 uint32_t address = (uint32_t)&base->FIFOWR; in USART_TransferSendDMA()
Dfsl_usart.h602 base->FIFOWR = data; in USART_WriteByte()
/hal_nxp-2.7.6/mcux/drivers/lpc/
Dfsl_i2s.c820 base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); in I2S_TxHandleIRQ()
830 base->FIFOWR = (data & 0xFFU); in I2S_TxHandleIRQ()
837 base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); in I2S_TxHandleIRQ()
848 base->FIFOWR = data & 0xFFFFU; in I2S_TxHandleIRQ()
855 base->FIFOWR = data; in I2S_TxHandleIRQ()
875 base->FIFOWR = *((volatile uint32_t *)(dataAddr)); in I2S_TxHandleIRQ()
894 base->FIFOWR = data; in I2S_TxHandleIRQ()
903 base->FIFOWR = *((volatile uint32_t *)(dataAddr)); in I2S_TxHandleIRQ()
948 base->FIFOWR = 0U; in I2S_TxHandleIRQ()
954 base->FIFOWR = 0U; in I2S_TxHandleIRQ()
Dfsl_i2s_dma.c297 base->FIFOWR = 0U; in I2S_TransferAbortDMA()
457 destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); in I2S_StartTransferDMA()
502 …((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_Dummy… in I2S_StartTransferDMA()
552 destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); in I2S_AddTransferDMA()
Dfsl_spi_dma.c278 address = (uint32_t)&base->FIFOWR; in SPI_MasterTransferDMA()
392 *((uint16_t *)((uint32_t)&base->FIFOWR) + 1) = (uint16_t)(tmpData >> 16U); in SPI_MasterTransferDMA()
398 *((uint16_t *)((uint32_t)&base->FIFOWR) + 1) = (uint16_t)(tmpData >> 16U); in SPI_MasterTransferDMA()
Dfsl_usart.c492 base->FIFOWR = ((uint32_t)address | 0x100UL); in USART_SendAddress()
541 base->FIFOWR = *data; in USART_WriteBlocking()
1115 base->FIFOWR = *handle->txData; in USART_TransferHandleIRQ()
Dfsl_spi.c453 base->FIFOWR = data | control; in SPI_WriteData()
624 base->FIFOWR = tmp32; in SPI_MasterTransferBlocking()
980 base->FIFOWR = tmp32; in SPI_TransferHandleIRQInternal()
Dfsl_usart_dma.c203 uint32_t address = (uint32_t)&base->FIFOWR; in USART_TransferSendDMA()
Dfsl_usart.h602 base->FIFOWR = data; in USART_WriteByte()
/hal_nxp-2.7.6/mcux/devices/LPC54114/
DLPC54114_cm0plus.h3909 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
7274 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
10364 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
DLPC54114_cm4.h3920 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
7285 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
10377 __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
/hal_nxp-2.7.6/mcux/devices/LPC55S28/
DLPC55S28.h11473 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
19201 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
24187 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
/hal_nxp-2.7.6/mcux/devices/LPC55S69/
DLPC55S69_cm33_core0.h11473 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
19799 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
24819 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
DLPC55S69_cm33_core1.h11473 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
19799 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
24819 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
/hal_nxp-2.7.6/mcux/devices/LPC55S16/
DLPC55S16.h13112 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
19541 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
24094 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
/hal_nxp-2.7.6/mcux/devices/MIMXRT685S/
DMIMXRT685S_dsp.h9656 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
20762 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
29053 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
DMIMXRT685S_cm33.h14827 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
27472 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member
34931 __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ member