1 /*
2 * Copyright 2020-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_ENET_QOS_H_
8 #define _FSL_ENET_QOS_H_
9
10 #include "fsl_common.h"
11 #include "fsl_cache.h"
12 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
13 #include "fsl_memory.h"
14 #endif
15 /*!
16 * @addtogroup enet_qos_qos
17 * @{
18 */
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 /*! @brief Defines the driver version. */
27 #define FSL_ENET_QOS_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
28 /*@}*/
29
30 /*! @name Control and status region bit masks of the receive buffer descriptor. */
31 /*@{*/
32 /*! @brief Defines for read format. */
33 #define ENET_QOS_RXDESCRIP_RD_BUFF1VALID_MASK (1UL << 24U) /*!< Buffer1 address valid. */
34 #define ENET_QOS_RXDESCRIP_RD_BUFF2VALID_MASK (1UL << 25U) /*!< Buffer2 address valid. */
35 #define ENET_QOS_RXDESCRIP_RD_IOC_MASK (1UL << 30U) /*!< Interrupt enable on complete. */
36 #define ENET_QOS_RXDESCRIP_RD_OWN_MASK (1UL << 31U) /*!< Own bit. */
37
38 /*! @brief Defines for write back format. */
39 #define ENET_QOS_RXDESCRIP_WR_ERR_MASK ((1UL << 3U) | (1UL << 7U))
40 #define ENET_QOS_RXDESCRIP_WR_PYLOAD_MASK (0x7UL)
41 #define ENET_QOS_RXDESCRIP_WR_PTPMSGTYPE_MASK (0xF00UL)
42 #define ENET_QOS_RXDESCRIP_WR_PTPTYPE_MASK (1UL << 12U)
43 #define ENET_QOS_RXDESCRIP_WR_PTPVERSION_MASK (1UL << 13U)
44 #define ENET_QOS_RXDESCRIP_WR_PTPTSA_MASK (1UL << 14U)
45 #define ENET_QOS_RXDESCRIP_WR_PACKETLEN_MASK (0x7FFFUL)
46 #define ENET_QOS_RXDESCRIP_WR_ERRSUM_MASK (1UL << 15U)
47 #define ENET_QOS_RXDESCRIP_WR_TYPE_MASK (0x30000UL)
48 #define ENET_QOS_RXDESCRIP_WR_DE_MASK (1UL << 19U)
49 #define ENET_QOS_RXDESCRIP_WR_RE_MASK (1UL << 20U)
50 #define ENET_QOS_RXDESCRIP_WR_OE_MASK (1UL << 21U)
51 #define ENET_QOS_RXDESCRIP_WR_RWT_MASK (1UL << 22U)
52 #define ENET_QOS_RXDESCRIP_WR_GP_MASK (1UL << 22U)
53 #define ENET_QOS_RXDESCRIP_WR_CRC_MASK (1UL << 23U)
54 #define ENET_QOS_RXDESCRIP_WR_RS0V_MASK (1UL << 25U)
55 #define ENET_QOS_RXDESCRIP_WR_RS1V_MASK (1UL << 26U)
56 #define ENET_QOS_RXDESCRIP_WR_RS2V_MASK (1UL << 27U)
57 #define ENET_QOS_RXDESCRIP_WR_LD_MASK (1UL << 28U)
58 #define ENET_QOS_RXDESCRIP_WR_FD_MASK (1UL << 29U)
59 #define ENET_QOS_RXDESCRIP_WR_CTXT_MASK (1UL << 30U)
60 #define ENET_QOS_RXDESCRIP_WR_OWN_MASK (1UL << 31U)
61
62 #define ENET_QOS_RXDESCRIP_WR_SA_FAILURE_MASK (1UL << 16U)
63 #define ENET_QOS_RXDESCRIP_WR_DA_FAILURE_MASK (1UL << 17U)
64 /*@}*/
65
66 /*! @name Control and status bit masks of the transmit buffer descriptor. */
67 /*@{*/
68 /*! @brief Defines for read format. */
69 #define ENET_QOS_TXDESCRIP_RD_BL1_MASK (0x3fffUL)
70 #define ENET_QOS_TXDESCRIP_RD_BL2_MASK (ENET_QOS_TXDESCRIP_RD_BL1_MASK << 16U)
71 #define ENET_QOS_TXDESCRIP_RD_BL1(n) ((uint32_t)(n)&ENET_QOS_TXDESCRIP_RD_BL1_MASK)
72 #define ENET_QOS_TXDESCRIP_RD_BL2(n) (((uint32_t)(n)&ENET_QOS_TXDESCRIP_RD_BL1_MASK) << 16)
73 #define ENET_QOS_TXDESCRIP_RD_TTSE_MASK (1UL << 30UL)
74 #define ENET_QOS_TXDESCRIP_RD_IOC_MASK (1UL << 31UL)
75
76 #define ENET_QOS_TXDESCRIP_RD_FL_MASK (0x7FFFUL)
77 #define ENET_QOS_TXDESCRIP_RD_FL(n) ((uint32_t)(n)&ENET_QOS_TXDESCRIP_RD_FL_MASK)
78 #define ENET_QOS_TXDESCRIP_RD_CIC(n) (((uint32_t)(n)&0x3U) << 16U)
79 #define ENET_QOS_TXDESCRIP_RD_TSE_MASK (1UL << 18U)
80 #define ENET_QOS_TXDESCRIP_RD_SLOT(n) (((uint32_t)(n)&0x0fU) << 19U)
81 #define ENET_QOS_TXDESCRIP_RD_SAIC(n) (((uint32_t)(n)&0x07U) << 23U)
82 #define ENET_QOS_TXDESCRIP_RD_CPC(n) (((uint32_t)(n)&0x03U) << 26U)
83 #define ENET_QOS_TXDESCRIP_RD_LDFD(n) (((uint32_t)(n)&0x03U) << 28U)
84 #define ENET_QOS_TXDESCRIP_RD_LD_MASK (1UL << 28U)
85 #define ENET_QOS_TXDESCRIP_RD_FD_MASK (1UL << 29U)
86 #define ENET_QOS_TXDESCRIP_RD_CTXT_MASK (1UL << 30U)
87 #define ENET_QOS_TXDESCRIP_RD_OWN_MASK (1UL << 31U)
88
89 /*! @brief Defines for write back format. */
90 #define ENET_QOS_TXDESCRIP_WB_TTSS_MASK (1UL << 17U)
91 /*@}*/
92
93 /*! @name Bit mask for interrupt enable type. */
94 /*@{*/
95 #define ENET_QOS_ABNORM_INT_MASK \
96 (ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK | ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RSE_MASK | \
97 ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK | ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK | ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
98 #define ENET_QOS_NORM_INT_MASK \
99 (ENET_QOS_DMA_CHX_INT_EN_TIE_MASK | ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK | ENET_QOS_DMA_CHX_INT_EN_RIE_MASK | \
100 ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
101 /*@}*/
102
103 /*! @name Defines some Ethernet parameters. */
104 /*@{*/
105 #ifndef ENET_QOS_RING_NUM_MAX
106 #define ENET_QOS_RING_NUM_MAX (5U) /*!< The Maximum number of tx/rx descriptor rings. */
107 #endif
108 #define ENET_QOS_FRAME_MAX_FRAMELEN (1518U) /*!< Default maximum Ethernet frame size. */
109 #define ENET_QOS_FCS_LEN (4U) /*!< Ethernet FCS length. */
110 #define ENET_QOS_ADDR_ALIGNMENT (0x3U) /*!< Recommended Ethernet buffer alignment. */
111 #define ENET_QOS_BUFF_ALIGNMENT (8U) /*!< Receive buffer alignment shall be 4bytes-aligned. */
112 #define ENET_QOS_MTL_RXFIFOSIZE (8192U) /*!< The rx fifo size. */
113 #define ENET_QOS_MTL_TXFIFOSIZE (8192U) /*!< The tx fifo size. */
114 #define ENET_QOS_MACINT_ENUM_OFFSET (16U) /*!< The offest for mac interrupt in enum type. */
115 #define ENET_QOS_RXP_ENTRY_COUNT (256U) /*!< RXP table entry count, implied by FRPES in MAC_HW_FEATURE3 */
116 #define ENET_QOS_RXP_BUFFER_SIZE (256U) /*!< RXP Buffer size, implied by FRPBS in MAC_HW_FEATURE3 */
117 #define ENET_QOS_EST_WID (24U) /*!< Width of the time interval in Gate Control List */
118 #define ENET_QOS_EST_DEP (512U) /*!< Maxmimum depth of Gate Control List */
119 /*@}*/
120
121 /*! @brief Defines the status return codes for transaction. */
122 enum
123 {
124 kStatus_ENET_QOS_InitMemoryFail =
125 MAKE_STATUS(kStatusGroup_ENET_QOS, 0U), /*!< Init fails since buffer memory is not enough. */
126 kStatus_ENET_QOS_RxFrameError =
127 MAKE_STATUS(kStatusGroup_ENET_QOS, 1U), /*!< A frame received but data error happen. */
128 kStatus_ENET_QOS_RxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 2U), /*!< Failed to receive a frame. */
129 kStatus_ENET_QOS_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET_QOS, 3U), /*!< No frame arrive. */
130 kStatus_ENET_QOS_RxFrameDrop =
131 MAKE_STATUS(kStatusGroup_ENET_QOS, 4U), /*!< Rx frame is dropped since no buffer memory. */
132 kStatus_ENET_QOS_TxFrameBusy =
133 MAKE_STATUS(kStatusGroup_ENET_QOS, 5U), /*!< Transmit descriptors are under process. */
134 kStatus_ENET_QOS_TxFrameFail = MAKE_STATUS(kStatusGroup_ENET_QOS, 6U), /*!< Transmit frame fail. */
135 kStatus_ENET_QOS_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET_QOS, 7U), /*!< Transmit oversize. */
136 kStatus_ENET_QOS_Est_SwListBusy =
137 MAKE_STATUS(kStatusGroup_ENET_QOS, 8U), /*!< SW Gcl List not yet processed by HW. */
138 kStatus_ENET_QOS_Est_SwListWriteAbort = MAKE_STATUS(kStatusGroup_ENET_QOS, 9U), /*!< SW Gcl List write aborted .*/
139 kStatus_ENET_QOS_Est_InvalidParameter =
140 MAKE_STATUS(kStatusGroup_ENET_QOS, 10U), /*!< Invalid parameter in Gcl List .*/
141 kStatus_ENET_QOS_Est_BtrError = MAKE_STATUS(kStatusGroup_ENET_QOS, 11U), /*!< Base Time Error when loading list.*/
142 kStatus_ENET_QOS_TrgtBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 12U), /*!< Target time register busy.*/
143 kStatus_ENET_QOS_Timeout = MAKE_STATUS(kStatusGroup_ENET_QOS, 13U), /*!< Target time register busy.*/
144 kStatus_ENET_QOS_PpsBusy = MAKE_STATUS(kStatusGroup_ENET_QOS, 14U) /*!< Pps command busy.*/
145 };
146
147 /*! @brief Defines the MII/RGMII mode for data interface between the MAC and the PHY. */
148 typedef enum _enet_qos_mii_mode
149 {
150 kENET_QOS_MiiMode = 0U, /*!< MII mode for data interface. */
151 kENET_QOS_RgmiiMode = 1U, /*!< RGMII mode for data interface. */
152 kENET_QOS_RmiiMode = 4U /*!< RMII mode for data interface. */
153 } enet_qos_mii_mode_t;
154
155 /*! @brief Defines the 10/100/1000 Mbps speed for the MII data interface. */
156 typedef enum _enet_qos_mii_speed
157 {
158 kENET_QOS_MiiSpeed10M =
159 ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 10 Mbps. */
160 kENET_QOS_MiiSpeed100M =
161 ENET_QOS_MAC_CONFIGURATION_PS(1U) | ENET_QOS_MAC_CONFIGURATION_FES(1U), /*!< Speed 100 Mbps. */
162 kENET_QOS_MiiSpeed1000M =
163 ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(0U), /*!< Speed 1000 Mbps. */
164 kENET_QOS_MiiSpeed2500M =
165 ENET_QOS_MAC_CONFIGURATION_PS(0U) | ENET_QOS_MAC_CONFIGURATION_FES(1U) /*!< Speed 2500 Mbps. */
166 } enet_qos_mii_speed_t;
167
168 /*! @brief Defines the half or full duplex for the MII data interface. */
169 typedef enum _enet_qos_mii_duplex
170 {
171 kENET_QOS_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
172 kENET_QOS_MiiFullDuplex /*!< Full duplex mode. */
173 } enet_qos_mii_duplex_t;
174
175 /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
176 typedef enum _enet_qos_mii_normal_opcode
177 {
178 kENET_QOS_MiiWriteFrame =
179 ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(0U) |
180 ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U), /*!< Write frame operation for a valid MII management frame. */
181 kENET_QOS_MiiReadFrame =
182 ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(1U) |
183 ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(1U) /*!< Read frame operation for a valid MII management frame. */
184 } enet_qos_mii_normal_opcode;
185
186 /*! @brief Define the DMA maximum transmit burst length. */
187 typedef enum _enet_qos_dma_burstlen
188 {
189 kENET_QOS_BurstLen1 = 0x00001U, /*!< DMA burst length 1. */
190 kENET_QOS_BurstLen2 = 0x00002U, /*!< DMA burst length 2. */
191 kENET_QOS_BurstLen4 = 0x00004U, /*!< DMA burst length 4. */
192 kENET_QOS_BurstLen8 = 0x00008U, /*!< DMA burst length 8. */
193 kENET_QOS_BurstLen16 = 0x00010U, /*!< DMA burst length 16. */
194 kENET_QOS_BurstLen32 = 0x00020U, /*!< DMA burst length 32. */
195 kENET_QOS_BurstLen64 = 0x10008U, /*!< DMA burst length 64. eight times enabled. */
196 kENET_QOS_BurstLen128 = 0x10010U, /*!< DMA burst length 128. eight times enabled. */
197 kENET_QOS_BurstLen256 = 0x10020U, /*!< DMA burst length 256. eight times enabled. */
198 } enet_qos_dma_burstlen;
199
200 /*! @brief Define the flag for the descriptor. */
201 typedef enum _enet_qos_desc_flag
202 {
203 kENET_QOS_MiddleFlag = 0, /*!< It's a middle descriptor of the frame. */
204 kENET_QOS_LastFlagOnly, /*!< It's the last descriptor of the frame. */
205 kENET_QOS_FirstFlagOnly, /*!< It's the first descriptor of the frame. */
206 kENET_QOS_FirstLastFlag /*!< It's the first and last descriptor of the frame. */
207 } enet_qos_desc_flag;
208
209 /*! @brief Define the system time adjust operation control. */
210 typedef enum _enet_qos_systime_op
211 {
212 kENET_QOS_SystimeAdd = 0U, /*!< System time add to. */
213 kENET_QOS_SystimeSubtract = 1U /*!< System time subtract. */
214 } enet_qos_systime_op;
215
216 /*! @brief Define the system time rollover control. */
217 typedef enum _enet_qos_ts_rollover_type
218 {
219 kENET_QOS_BinaryRollover = 0, /*!< System time binary rollover.*/
220 kENET_QOS_DigitalRollover = 1 /*!< System time digital rollover.*/
221 } enet_qos_ts_rollover_type;
222
223 /*! @brief Defines some special configuration for ENET.
224 *
225 * These control flags are provided for special user requirements.
226 * Normally, these is no need to set this control flags for ENET initialization.
227 * But if you have some special requirements, set the flags to specialControl
228 * in the enet_qos_config_t.
229 * @note "kENET_QOS_StoreAndForward" is recommended to be set.
230 */
231 typedef enum _enet_qos_special_config
232 {
233
234 /***********************DMA CONFGI**********************************************/
235 kENET_QOS_DescDoubleBuffer = 0x0001U, /*!< The double buffer is used in the tx/rx descriptor. */
236 /**************************MTL************************************/
237 kENET_QOS_StoreAndForward = 0x0002U, /*!< The rx/tx store and forward enable. */
238 /***********************MAC****************************************/
239 kENET_QOS_PromiscuousEnable = 0x0004U, /*!< The promiscuous enabled. */
240 kENET_QOS_FlowControlEnable = 0x0008U, /*!< The flow control enabled. */
241 kENET_QOS_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
242 kENET_QOS_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
243 kENET_QOS_8023AS2KPacket = 0x0040U, /*!< 8023as support for 2K packets. */
244 kENET_QOS_HashMulticastEnable = 0x0080U /*!< The multicast packets are filtered through hash table. */
245 } enet_qos_special_config_t;
246
247 /*! @brief List of DMA interrupts supported by the ENET interrupt. This
248 * enumeration uses one-bot encoding to allow a logical OR of multiple
249 * members.
250 */
251 typedef enum _enet_qos_dma_interrupt_enable
252 {
253 kENET_QOS_DmaTx = ENET_QOS_DMA_CHX_INT_EN_TIE_MASK, /*!< Tx interrupt. */
254 kENET_QOS_DmaTxStop = ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK, /*!< Tx stop interrupt. */
255 kENET_QOS_DmaTxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK, /*!< Tx buffer unavailable. */
256 kENET_QOS_DmaRx = ENET_QOS_DMA_CHX_INT_EN_RIE_MASK, /*!< Rx interrupt. */
257 kENET_QOS_DmaRxBuffUnavail = ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK, /*!< Rx buffer unavailable. */
258 kENET_QOS_DmaRxStop = ENET_QOS_DMA_CHX_INT_EN_RSE_MASK, /*!< Rx stop. */
259 kENET_QOS_DmaRxWatchdogTimeout = ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK, /*!< Rx watchdog timeout. */
260 kENET_QOS_DmaEarlyTx = ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK, /*!< Early transmit. */
261 kENET_QOS_DmaEarlyRx = ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK, /*!< Early receive. */
262 kENET_QOS_DmaBusErr = ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK, /*!< Fatal bus error. */
263 } enet_qos_dma_interrupt_enable_t;
264
265 /*! @brief List of mac interrupts supported by the ENET interrupt. This
266 * enumeration uses one-bot encoding to allow a logical OR of multiple
267 * members.
268 */
269 typedef enum _enet_qos_mac_interrupt_enable
270 {
271 kENET_QOS_MacPmt = (ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
272 kENET_QOS_MacTimestamp = (ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK << ENET_QOS_MACINT_ENUM_OFFSET),
273 } enet_qos_mac_interrupt_enable_t;
274
275 /*! @brief Defines the common interrupt event for callback use. */
276 typedef enum _enet_qos_event
277 {
278 kENET_QOS_RxIntEvent, /*!< Receive interrupt event. */
279 kENET_QOS_TxIntEvent, /*!< Transmit interrupt event. */
280 kENET_QOS_WakeUpIntEvent, /*!< Wake up interrupt event. */
281 kENET_QOS_TimeStampIntEvent, /*!< Time stamp interrupt event. */
282 } enet_qos_event_t;
283
284 /*! @brief Define the MTL mode for multiple queues/rings. */
285 typedef enum _enet_qos_queue_mode
286 {
287 kENET_QOS_AVB_Mode = 1U, /*!< Enable queue in AVB mode. */
288 kENET_QOS_DCB_Mode = 2U, /*!< Enable queue in DCB mode. */
289 } enet_qos_queue_mode_t;
290
291 /*! @brief Define the MTL tx scheduling algorithm for multiple queues/rings. */
292 typedef enum _enet_qos_mtl_multiqueue_txsche
293 {
294 kENET_QOS_txWeightRR = 0U, /*!< Tx weight round-robin. */
295 kENET_QOS_txWeightFQ = 1U, /*!< Tx weight fair queuing. */
296 kENET_QOS_txDefictWeightRR = 2U, /*!< Tx deficit weighted round-robin. */
297 kENET_QOS_txStrPrio = 3U, /*!< Tx strict priority. */
298 } enet_qos_mtl_multiqueue_txsche;
299
300 /*! @brief Define the MTL rx scheduling algorithm for multiple queues/rings. */
301 typedef enum _enet_qos_mtl_multiqueue_rxsche
302 {
303 kENET_QOS_rxStrPrio = 0U, /*!< Rx strict priority, Queue 0 has the lowest priority. */
304 kENET_QOS_rxWeightStrPrio, /*!< Weighted Strict Priority. */
305 } enet_qos_mtl_multiqueue_rxsche;
306
307 /*! @brief Define the MTL rx queue and DMA channel mapping. */
308 typedef enum _enet_qos_mtl_rxqueuemap
309 {
310 kENET_QOS_StaticDirctMap = 0x100U, /*!< The received fame in rx Qn(n = 0,1) directly map to dma channel n. */
311 kENET_QOS_DynamicMap =
312 0x1010U, /*!< The received frame in rx Qn(n = 0,1) map to the dma channel m(m = 0,1) related with the same Mac.
313 */
314 } enet_qos_mtl_rxqueuemap_t;
315
316 /*! @brief Defines the package type for receive queue routing. */
317 typedef enum _enet_qos_rx_queue_route
318 {
319 kENET_QOS_PacketNoQ = 0x0, /* Not specific queue */
320 kENET_QOS_PacketAVCPQ = (1U << 0U), /* AV Untagged Control Packets Queue */
321 kENET_QOS_PacketPTPQ = (1U << 1U), /* PTP Packets Queue */
322 kENET_QOS_PacketDCBCPQ = (1U << 2U), /* DCB Control Packets Queue */
323 kENET_QOS_PacketUPQ = (1U << 3U), /* Untagged Packets Queue */
324 kENET_QOS_PacketMCBCQ = (1U << 4U), /* Multicast & Broadcast Packets Queue */
325 } enet_qos_rx_queue_route_t;
326
327 /*! @brief Defines the ENET PTP message related constant. */
328 typedef enum _enet_qos_ptp_event_type
329 {
330 kENET_QOS_PtpEventMsgType = 3U, /*!< PTP event message type. */
331 kENET_QOS_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
332 kENET_QOS_PtpEventPort = 319U, /*!< PTP event port number. */
333 kENET_QOS_PtpGnrlPort = 320U /*!< PTP general port number. */
334 } enet_qos_ptp_event_type_t;
335
336 /*! @brief Defines the PPS instance numbers. */
337 typedef enum _enet_qos_ptp_pps_instance
338 {
339 kENET_QOS_PtpPpsIstance0 = 0U, /*!< PPS instance 0. */
340 kENET_QOS_PtpPpsIstance1, /*!< PPS instance 1. */
341 kENET_QOS_PtpPpsIstance2, /*!< PPS instance 2. */
342 kENET_QOS_PtpPpsIstance3 /*!< PPS instance 3. */
343 } enet_qos_ptp_pps_instance_t;
344
345 /*! @brief Defines the Target Time register mode. */
346 typedef enum _enet_qos_ptp_pps_trgt_mode
347 {
348 kENET_QOS_PtpPpsTrgtModeOnlyInt = 0U, /*!< Only interrupts. */
349 kENET_QOS_PtpPpsTrgtModeIntSt = 2, /*!< Both interrupt and output signal. */
350 kENET_QOS_PtpPpsTrgtModeOnlySt = 3, /*!< Only output signal. */
351 } enet_qos_ptp_pps_trgt_mode_t;
352
353 /*! @brief Defines commands for ppscmd register. */
354 typedef enum _enet_qos_ptp_pps_cmd
355 {
356 kENET_QOS_PtpPpsCmdNC = 0U, /*!< No Command. */
357 kENET_QOS_PtpPpsCmdSSP = 1U, /*!< Start Single Pulse. */
358 kENET_QOS_PtpPpsCmdSPT = 2U, /*!< Start Pulse Train. */
359 kENET_QOS_PtpPpsCmdCS = 3U, /*!< Cancel Start. */
360 kENET_QOS_PtpPpsCmdSPTAT = 4U, /*!< Stop Pulse Train At Time. */
361 kENET_QOS_PtpPpsCmdSPTI = 5U, /*!< Stop Pulse Train Immediately. */
362 kENET_QOS_PtpPpsCmdCSPT = 6U, /*!< Cancel Stop Pulse Train. */
363 } enet_qos_ptp_pps_cmd_t;
364
365 /*! @brief Defines the enmueration of ETS list length.
366 */
367 typedef enum _enet_qos_ets_list_length
368 {
369 kENET_QOS_Ets_List_64 = 7U, /*!< List length of 64 */
370 kENET_QOS_Ets_List_128 = 8U, /*!< List length of 128 */
371 kENET_QOS_Ets_List_256 = 9U, /*!< List length of 256 */
372 kENET_QOS_Ets_List_512 = 10U, /*!< List length of 512 */
373 kENET_QOS_Ets_List_1024 = 11U, /*!< List length of 1024 */
374 } enet_qos_ets_list_length_t;
375
376 /*! @brief Defines the enmueration of ETS gate control address.
377 */
378 typedef enum _enet_qos_ets_gccr_addr
379 {
380 kENET_QOS_Ets_btr_low = 0U, /*!< BTR Low */
381 kENET_QOS_Ets_btr_high = 1U, /*!< BTR High */
382 kENET_QOS_Ets_ctr_low = 2U, /*!< CTR Low */
383 kENET_QOS_Ets_ctr_high = 3U, /*!< CTR High */
384 kENET_QOS_Ets_ter = 4U, /*!< TER */
385 kENET_QOS_Ets_llr = 5U, /*!< LLR */
386 } enet_qos_ets_gccr_addr_t;
387
388 /*! @brief Defines the enmueration of DMA channel used
389 * for rx parser entry.
390 */
391 typedef enum _enet_qos_rxp_dma_chn
392 {
393 kENET_QOS_Rxp_DMAChn0 = 1U, /*!< DMA Channel 0 used for RXP entry match */
394 kENET_QOS_Rxp_DMAChn1 = 2U, /*!< DMA Channel 1 used for RXP entry match */
395 kENET_QOS_Rxp_DMAChn2 = 4U, /*!< DMA Channel 2 used for RXP entry match */
396 kENET_QOS_Rxp_DMAChn3 = 8U, /*!< DMA Channel 3 used for RXP entry match */
397 kENET_QOS_Rxp_DMAChn4 = 16U, /*!< DMA Channel 4 used for RXP entry match */
398 } enet_qos_rxp_dma_chn_t;
399
400 /*! @brief Defines the receive descriptor structure
401 * has the read-format and write-back format structure. They both
402 * has the same size with different region definition. so
403 * we define the read-format region as the receive descriptor structure
404 * Use the read-format region mask bits in the descriptor initialization
405 * Use the write-back format region mask bits in the receive data process.
406 */
407 typedef struct _enet_qos_rx_bd_struct
408 {
409 __IO uint32_t buff1Addr; /*!< Buffer 1 address */
410 __IO uint32_t reserved; /*!< Reserved */
411 __IO uint32_t buff2Addr; /*!< Buffer 2 or next descriptor address */
412 __IO uint32_t control; /*!< Buffer 1/2 byte counts and control */
413 } enet_qos_rx_bd_struct_t;
414
415 /*! @brief Defines the transmit descriptor structure
416 * has the read-format and write-back format structure. They both
417 * has the same size with different region definition. so
418 * we define the read-format region as the transmit descriptor structure
419 * Use the read-format region mask bits in the descriptor initialization
420 * Use the write-back format region mask bits in the transmit data process.
421 */
422 typedef struct _enet_qos_tx_bd_struct
423 {
424 __IO uint32_t buff1Addr; /*!< Buffer 1 address */
425 __IO uint32_t buff2Addr; /*!< Buffer 2 address */
426 __IO uint32_t buffLen; /*!< Buffer 1/2 byte counts */
427 __IO uint32_t controlStat; /*!< TDES control and status word */
428 } enet_qos_tx_bd_struct_t;
429
430 /*! @brief Defines the ENET PTP time stamp structure. */
431 typedef struct _enet_qos_ptp_time
432 {
433 uint64_t second; /*!< Second. */
434 uint32_t nanosecond; /*!< Nanosecond. */
435 } enet_qos_ptp_time_t;
436
437 /*! @brief Defines the frame info structure. */
438 typedef struct enet_qos_frame_info
439 {
440 void *context; /*!< User specified data, could be buffer address for free */
441 bool isTsAvail; /*!< Flag indicates timestamp available status */
442 enet_qos_ptp_time_t timeStamp; /*!< Timestamp of frame */
443 } enet_qos_frame_info_t;
444
445 /*! @brief Defines the ENET transmit dirty addresses ring/queue structure. */
446 typedef struct _enet_qos_tx_dirty_ring
447 {
448 enet_qos_frame_info_t *txDirtyBase; /*!< Dirty buffer descriptor base address pointer. */
449 uint16_t txGenIdx; /*!< tx generate index. */
450 uint16_t txConsumIdx; /*!< tx consume index. */
451 uint16_t txRingLen; /*!< tx ring length. */
452 bool isFull; /*!< tx ring is full flag, add this parameter to avoid waste one element. */
453 } enet_qos_tx_dirty_ring_t;
454
455 /*! @brief Defines the ENET PTP configuration structure. */
456 typedef struct _enet_qos_ptp_config
457 {
458 bool fineUpdateEnable; /*!< Use the fine update. */
459 uint32_t defaultAddend; /*!< Default addend value when fine update is enable, could be 2^32 / (refClk_Hz /
460 ENET_QOS_MICRSECS_ONESECOND / ENET_QOS_SYSTIME_REQUIRED_CLK_MHZ). */
461 uint32_t systemTimeClock_Hz; /*! The desired system time frequency. Must be lower than reference clock. (Only used
462 with fine correction method). */
463 bool ptp1588V2Enable; /*!< ptp 1588 version 2 is used. */
464 enet_qos_ts_rollover_type tsRollover; /*!< 1588 time nanosecond rollover. */
465 } enet_qos_ptp_config_t;
466
467 /*! @brief Defines the EST gate operation structure. */
468 typedef struct _enet_qos_est_gate_op
469 {
470 uint32_t gate;
471 uint32_t interval;
472 } enet_qos_est_gate_op_t;
473
474 /*! @brief Defines the EST gate control list structure. */
475 typedef struct _enet_qos_est_gcl
476 {
477 bool enable; /*!< Enable or disable EST */
478 uint64_t baseTime; /*! Base Time 32 bits seconds 32 bits nanoseconds */
479 uint64_t cycleTime; /*! Cycle Time 32 bits seconds 32 bits nanoseconds */
480 uint32_t extTime; /*! Time Extension 32 bits seconds 32 bits nanoseconds */
481 uint32_t numEntries; /*! Number of entries */
482 enet_qos_est_gate_op_t *opList; /*! Pointer to GCL list size */
483 } enet_qos_est_gcl_t;
484
485 /*! @brief Defines the ENET_QOS Rx parser configuration structure.*/
486 typedef struct _enet_qos_rxp_config
487 {
488 uint32_t matchData; /*! 4-byte match data used for comparing with incoming packet */
489 uint32_t matchEnable; /*! When matchEnable is set to 1, the matchData is used for comparing */
490 uint8_t acceptFrame : 1; /*! When acceptFrame = 1 and data is matched, the frame will be sent to DMA channel */
491 uint8_t rejectFrame : 1; /*! When rejectFrame = 1 and data is matched, the frame will be dropped */
492 uint8_t inverseMatch : 1; /*! Inverse match */
493 uint8_t nextControl : 1; /*! Next instruction indexing control */
494 uint8_t reserved : 4; /*! Reserved control fields */
495 uint8_t frameOffset; /*! Frame offset in the packet data to be compared for match, in terms of 4 bytes. */
496 uint8_t okIndex; /*! Memory Index to be used next. */
497 uint8_t dmaChannel; /*! The DMA channel enet_qos_rxp_dma_chn_t used for receiving the frame when frame match and
498 acceptFrame = 1 */
499 uint32_t reserved2; /*! Reserved for future enhancements */
500 } enet_qos_rxp_config_t;
501
502 /*! @brief Defines the buffer descriptor configure structure.
503 *
504 * @note
505 * 1. The receive and transmit descriptor start address pointer and tail pointer must be word-aligned.
506 * 2. The recommended minimum tx/rx ring length is 4.
507 * 3. The tx/rx descriptor tail address shall be the address pointer to the address just after the end
508 * of the last last descriptor. because only the descriptors between the start address and the
509 * tail address will be used by DMA.
510 * 4. The descriptor address is the start address of all used contiguous memory.
511 * for example, the rxDescStartAddrAlign is the start address of rxRingLen contiguous descriptor memories
512 * for rx descriptor ring 0.
513 * 5. The "*rxBufferstartAddr" is the first element of rxRingLen (2*rxRingLen for double buffers)
514 * rx buffers. It means the *rxBufferStartAddr is the rx buffer for the first descriptor
515 * the *rxBufferStartAddr + 1 is the rx buffer for the second descriptor or the rx buffer for
516 * the second buffer in the first descriptor. so please make sure the rxBufferStartAddr is the
517 * address of a rxRingLen or 2*rxRingLen array.
518 */
519 typedef struct _enet_qos_buffer_config
520 {
521 uint8_t rxRingLen; /*!< The length of receive buffer descriptor ring. */
522 uint8_t txRingLen; /*!< The length of transmit buffer descriptor ring. */
523 enet_qos_tx_bd_struct_t *txDescStartAddrAlign; /*!< Aligned transmit descriptor start address. */
524 enet_qos_tx_bd_struct_t *txDescTailAddrAlign; /*!< Aligned transmit descriptor tail address. */
525 enet_qos_frame_info_t *txDirtyStartAddr; /*!< Start address of the dirty tx frame information. */
526 enet_qos_rx_bd_struct_t *rxDescStartAddrAlign; /*!< Aligned receive descriptor start address. */
527 enet_qos_rx_bd_struct_t *rxDescTailAddrAlign; /*!< Aligned receive descriptor tail address. */
528 uint32_t *rxBufferStartAddr; /*!< Start address of the rx buffers. */
529 uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */
530 bool rxBuffNeedMaintain; /*!< Whether receive data buffer need cache maintain. */
531 } enet_qos_buffer_config_t;
532
533 /*! @brief Defines the CBS configuration for queue. */
534 typedef struct _enet_qos_cbs_config
535 {
536 uint16_t sendSlope; /*!< Send slope configuration. */
537 uint16_t idleSlope; /*!< Idle slope configuration. */
538 uint32_t highCredit; /*!< High credit. */
539 uint32_t lowCredit; /*!< Low credit. */
540 } enet_qos_cbs_config_t;
541
542 /*! @brief Defines the queue configuration structure. */
543 typedef struct enet_qos_tx_queue_config
544 {
545 enet_qos_queue_mode_t mode; /*!< tx queue mode configuration. */
546 uint32_t weight; /*!< Refer to the MTL TxQ Quantum Weight register. */
547 uint32_t priority; /*!< Refer to Transmit Queue Priority Mapping register. */
548 enet_qos_cbs_config_t *cbsConfig; /*!< CBS configuration if queue use AVB mode. */
549 } enet_qos_queue_tx_config_t;
550
551 /*! @brief Defines the queue configuration structure. */
552 typedef struct enet_qos_rx_queue_config
553 {
554 enet_qos_queue_mode_t mode; /*!< rx queue mode configuration. */
555 uint8_t mapChannel; /*!< tx queue map dma channel. */
556 uint32_t priority; /*!< Rx queue priority. */
557 enet_qos_rx_queue_route_t packetRoute; /*!< Receive packet routing. */
558 } enet_qos_queue_rx_config_t;
559
560 /*! @brief Defines the configuration when multi-queue is used. */
561 typedef struct enet_qos_multiqueue_config
562 {
563 enet_qos_dma_burstlen burstLen; /*!< Burst len for the multi-queue. */
564 uint8_t txQueueUse; /*!< Used Tx queue count. */
565 enet_qos_mtl_multiqueue_txsche mtltxSche; /*!< Transmit schedule for multi-queue. */
566 enet_qos_queue_tx_config_t txQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Tx Queue configuration. */
567 uint8_t rxQueueUse; /*!< Used Rx queue count. */
568 enet_qos_mtl_multiqueue_rxsche mtlrxSche; /*!< Receive schedule for multi-queue. */
569 enet_qos_queue_rx_config_t rxQueueConfig[ENET_QOS_RING_NUM_MAX]; /*!< Rx Queue configuration. */
570 } enet_qos_multiqueue_config_t;
571
572 /*! @brief Defines the Rx memory buffer alloc function pointer. */
573 typedef void *(*enet_qos_rx_alloc_callback_t)(ENET_QOS_Type *base, void *userData, uint8_t channel);
574
575 /*! @brief Defines the Rx memory buffer free function pointer. */
576 typedef void (*enet_qos_rx_free_callback_t)(ENET_QOS_Type *base, void *buffer, void *userData, uint8_t channel);
577
578 /*! @brief Defines the basic configuration structure for the ENET device.
579 *
580 * @note Default the signal queue is used so the "*multiqueueCfg" is set default
581 * with NULL. Set the pointer with a valid configuration pointer if the multiple
582 * queues are required. If multiple queue is enabled, please make sure the
583 * buffer configuration for all are prepared also.
584 */
585 typedef struct _enet_qos_config
586 {
587 uint16_t specialControl; /*!< The logic or of enet_qos_special_config_t */
588 enet_qos_multiqueue_config_t *multiqueueCfg; /*!< Use multi-queue. */
589 /* -----------------MAC block-------------------------------*/
590 enet_qos_mii_mode_t miiMode; /*!< MII mode. */
591 enet_qos_mii_speed_t miiSpeed; /*!< MII Speed. */
592 enet_qos_mii_duplex_t miiDuplex; /*!< MII duplex. */
593 uint16_t
594 pauseDuration; /*!< Used in the tx flow control frame, only valid when kENET_QOS_FlowControlEnable is set. */
595 /* -----------------Timestamp -------------------------------*/
596 enet_qos_ptp_config_t *ptpConfig; /*!< PTP 1588 feature configuration */
597 uint32_t csrClock_Hz; /*!< CSR clock frequency in HZ. */
598 enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
599 enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
600 } enet_qos_config_t;
601
602 /* Forward declaration of the handle typedef. */
603 typedef struct _enet_qos_handle enet_qos_handle_t;
604
605 /*! @brief ENET callback function. */
606 typedef void (*enet_qos_callback_t)(
607 ENET_QOS_Type *base, enet_qos_handle_t *handle, enet_qos_event_t event, uint8_t channel, void *userData);
608
609 /*! @brief Defines the ENET transmit buffer descriptor ring/queue structure. */
610 typedef struct _enet_qos_tx_bd_ring
611 {
612 enet_qos_tx_bd_struct_t *txBdBase; /*!< Buffer descriptor base address pointer. */
613 uint16_t txGenIdx; /*!< tx generate index. */
614 uint16_t txConsumIdx; /*!< tx consume index. */
615 volatile uint16_t txDescUsed; /*!< tx descriptor used number. */
616 uint16_t txRingLen; /*!< tx ring length. */
617 } enet_qos_tx_bd_ring_t;
618
619 /*! @brief Defines the ENET receive buffer descriptor ring/queue structure. */
620 typedef struct _enet_qos_rx_bd_ring
621 {
622 enet_qos_rx_bd_struct_t *rxBdBase; /*!< Buffer descriptor base address pointer. */
623 uint16_t rxGenIdx; /*!< The current available receive buffer descriptor pointer. */
624 uint16_t rxRingLen; /*!< Receive ring length. */
625 uint32_t rxBuffSizeAlign; /*!< Receive buffer size. */
626 } enet_qos_rx_bd_ring_t;
627
628 /*! @brief Defines the ENET handler structure. */
629 struct _enet_qos_handle
630 {
631 uint8_t txQueueUse; /*!< Used tx queue count. */
632 uint8_t rxQueueUse; /*!< Used rx queue count. */
633 bool doubleBuffEnable; /*!< The double buffer is used in the descriptor. */
634 bool rxintEnable; /*!< Rx interrupt enabled. */
635 bool rxMaintainEnable[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer cache maintain enabled. */
636 enet_qos_rx_bd_ring_t rxBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Receive buffer descriptor. */
637 enet_qos_tx_bd_ring_t txBdRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit buffer descriptor. */
638 enet_qos_tx_dirty_ring_t txDirtyRing[ENET_QOS_RING_NUM_MAX]; /*!< Transmit dirty buffers addresses. */
639 uint32_t *rxBufferStartAddr[ENET_QOS_RING_NUM_MAX]; /*!< Rx buffer start address for reInitialize. */
640 enet_qos_callback_t callback; /*!< Callback function. */
641 void *userData; /*!< Callback function parameter.*/
642 uint8_t multicastCount[64]; /*!< Multicast collisions counter */
643 enet_qos_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
644 enet_qos_rx_free_callback_t rxBuffFree; /*!< Callback to free memory, must be provided for zero-copy Rx. */
645 };
646
647 /*! @brief Defines the frame buffer structure. */
648 typedef struct _enet_qos_buffer_struct
649 {
650 void *buffer; /*!< The buffer store the whole or partial frame. */
651 uint16_t length; /*!< The byte length of this buffer. */
652 } enet_qos_buffer_struct_t;
653
654 /*! @brief Defines the Rx frame error structure. */
655 typedef struct _enet_qos_rx_frame_error
656 {
657 bool rxDstAddrFilterErr : 1; /*!< Destination Address Filter Fail. */
658 bool rxSrcAddrFilterErr : 1; /*!< SA Address Filter Fail. */
659 bool rxDribbleErr : 1; /*!< Dribble error. */
660 bool rxReceiveErr : 1; /*!< Receive error. */
661 bool rxOverFlowErr : 1; /*!< Receive over flow. */
662 bool rxWatchDogErr : 1; /*!< Watch dog timeout. */
663 bool rxGaintPacketErr : 1; /*!< Receive gaint packet. */
664 bool rxCrcErr : 1; /*!< Receive CRC error. */
665 } enet_qos_rx_frame_error_t;
666
667 typedef struct _enet_qos_rx_frame_attribute_struct
668 {
669 bool isTsAvail; /*!< Rx frame timestamp is available or not. */
670 enet_qos_ptp_time_t timestamp; /*!< The nanosecond part timestamp of this Rx frame. */
671 } enet_qos_rx_frame_attribute_t;
672
673 /*! @brief Defines the Rx frame data structure. */
674 typedef struct _enet_qos_rx_frame_struct
675 {
676 enet_qos_buffer_struct_t *rxBuffArray; /*!< Rx frame buffer structure. */
677 uint16_t totLen; /*!< Rx frame total length. */
678 enet_qos_rx_frame_attribute_t rxAttribute; /*!< Rx frame attribute structure. */
679 enet_qos_rx_frame_error_t rxFrameError; /*!< Rx frame error. */
680 } enet_qos_rx_frame_struct_t;
681
682 /*! @brief Defines the ENET QOS transfer statistics structure. */
683 typedef struct _enet_qos_transfer_stats
684 {
685 uint32_t statsRxFrameCount; /*!< Rx frame number. */
686 uint32_t statsRxCrcErr; /*!< Rx frame number with CRC error. */
687 uint32_t statsRxAlignErr; /*!< Rx frame number with alignment error. */
688 uint32_t statsRxLengthErr; /*!< Rx frame length field doesn't equal to packet size. */
689 uint32_t statsRxFifoOverflowErr; /*!< Rx FIFO overflow count. */
690 uint32_t statsTxFrameCount; /*!< Tx frame number. */
691 uint32_t statsTxFifoUnderRunErr; /*!< Tx FIFO underrun count. */
692 } enet_qos_transfer_stats_t;
693
694 /* Typedef for interrupt handler. */
695 typedef void (*enet_qos_isr_t)(ENET_QOS_Type *base, enet_qos_handle_t *handle);
696
697 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
698 /*! @brief Pointers to enet clocks for each instance. */
699 extern const clock_ip_name_t s_enetqosClock[];
700 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
701
702 /*!
703 * @brief Set ENET system configuration.
704 * @note User needs to provide the implementation because the implementation is SoC specific.
705 * This function set the phy selection and enable clock.
706 * It should be called before any other ethernet operation.
707 *
708 * @param miiMode The MII/RGMII/RMII mode for interface between the phy and Ethernet.
709 */
710 extern void ENET_QOS_SetSYSControl(enet_qos_mii_mode_t miiMode);
711
712 /*******************************************************************************
713 * API
714 ******************************************************************************/
715
716 #if defined(__cplusplus)
717 extern "C" {
718 #endif
719
720 /*!
721 * @name Initialization and De-initialization
722 * @{
723 */
724
725 /*!
726 * @brief Gets the ENET default configuration structure.
727 *
728 * The purpose of this API is to get the default ENET configure
729 * structure for @ref ENET_QOS_Init(). User may use the initialized
730 * structure unchanged in @ref ENET_QOS_Init(), or modify some fields of the
731 * structure before calling @ref ENET_QOS_Init().
732 * Example:
733 @code
734 enet_qos_config_t config;
735 ENET_QOS_GetDefaultConfig(&config);
736 @endcode
737 * @param config The ENET mac controller configuration structure pointer.
738 */
739 void ENET_QOS_GetDefaultConfig(enet_qos_config_t *config);
740
741 /*!
742 * @brief Initializes the ENET module.
743 *
744 * This function initializes it with the ENET basic
745 * configuration.
746 *
747 * @param base ENET peripheral base address.
748 * @param config ENET mac configuration structure pointer.
749 * The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
750 * can be used directly. It is also possible to verify the Mac configuration using other methods.
751 * @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
752 * provided.
753 * @param macCount Count of macAddr in the ENET mac address array
754 * @param refclkSrc_Hz ENET input reference clock.
755 */
756 status_t ENET_QOS_Up(
757 ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
758
759 /*!
760 * @brief Initializes the ENET module.
761 *
762 * This function ungates the module clock and initializes it with the ENET basic
763 * configuration.
764 *
765 * @param base ENET peripheral base address.
766 * @param config ENET mac configuration structure pointer.
767 * The "enet_qos_config_t" type mac configuration return from ENET_QOS_GetDefaultConfig
768 * can be used directly. It is also possible to verify the Mac configuration using other methods.
769 * @param macAddr Pointer to ENET mac address array of Ethernet device. This MAC address should be
770 * provided.
771 * @param macCount Count of macAddr in the ENET mac address array
772 * @param refclkSrc_Hz ENET input reference clock.
773 */
774 status_t ENET_QOS_Init(
775 ENET_QOS_Type *base, const enet_qos_config_t *config, uint8_t *macAddr, uint8_t macCount, uint32_t refclkSrc_Hz);
776
777 /*!
778 * @brief Stops the ENET module.
779
780 * This function disables the ENET module.
781 *
782 * @param base ENET peripheral base address.
783 */
784 void ENET_QOS_Down(ENET_QOS_Type *base);
785
786 /*!
787 * @brief Deinitializes the ENET module.
788
789 * This function gates the module clock and disables the ENET module.
790 *
791 * @param base ENET peripheral base address.
792 */
793 void ENET_QOS_Deinit(ENET_QOS_Type *base);
794
795 /*!
796 * @brief Get the ENET instance from peripheral base address.
797 *
798 * @param base ENET peripheral base address.
799 * @return ENET instance.
800 */
801 uint32_t ENET_QOS_GetInstance(ENET_QOS_Type *base);
802
803 /*!
804 * @brief Initialize for all ENET descriptors.
805 *
806 * @note This function is do all tx/rx descriptors initialization. Because this API
807 * read all interrupt registers first and then set the interrupt flag for all descriptors,
808 * if the interrupt register is set. so the descriptor initialization should be called
809 * after ENET_QOS_Init(), ENET_QOS_EnableInterrupts() and ENET_QOS_CreateHandle()(if transactional APIs
810 * are used).
811 *
812 * @param base ENET peripheral base address.
813 * @param config The configuration for ENET.
814 * @param bufferConfig All buffers configuration.
815 */
816 status_t ENET_QOS_DescriptorInit(ENET_QOS_Type *base,
817 enet_qos_config_t *config,
818 enet_qos_buffer_config_t *bufferConfig);
819
820 /*!
821 * @brief Allocates Rx buffers for all BDs.
822 * It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
823 * will populate initial buffers in all BDs for receiving. Then ENET_QOS_GetRxFrame() is used
824 * to get Rx frame with zero copy, it will allocate new buffer to replace the buffer in BD taken
825 * by application application should free those buffers after they're used.
826 *
827 * @note This function should be called after ENET_QOS_CreateHandler() and buffer allocating callback
828 * function should be ready.
829 *
830 * @param base ENET_QOS peripheral base address.
831 * @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
832 */
833 status_t ENET_QOS_RxBufferAllocAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
834
835 /*!
836 * @brief Frees Rx buffers in all BDs.
837 * It's used for zero copy Rx. In zero copy Rx case, Rx buffers are dynamic. This function
838 * will free left buffers in all BDs.
839 *
840 * @param base ENET_QOS peripheral base address.
841 * @param handle The ENET_QOS handler structure. This is the same handler pointer used in the ENET_QOS_Init.
842 */
843 void ENET_QOS_RxBufferFreeAll(ENET_QOS_Type *base, enet_qos_handle_t *handle);
844
845 /*!
846 * @brief Starts the ENET rx/tx.
847 * This function enable the tx/rx and starts the rx/tx DMA.
848 * This shall be set after ENET initialization and before
849 * starting to receive the data.
850 *
851 * @param base ENET peripheral base address.
852 * @param rxRingNum The number of the used rx rings. It shall not be
853 * larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
854 * 1, the ring 0 will be used.
855 * @param txRingNum The number of the used tx rings. It shall not be
856 * larger than the ENET_QOS_RING_NUM_MAX(2). If the ringNum is set with
857 * 1, the ring 0 will be used.
858 *
859 * @note This must be called after all the ENET initialization.
860 * And should be called when the ENET receive/transmit is required.
861 */
862 void ENET_QOS_StartRxTx(ENET_QOS_Type *base, uint8_t txRingNum, uint8_t rxRingNum);
863
864 /* @} */
865
866 /*!
867 * @name MII interface operation
868 * @{
869 */
870
871 /*!
872 * @brief Sets the ENET MII speed and duplex.
873 *
874 * This API is provided to dynamically change the speed and duplex for MAC.
875 *
876 * @param base ENET peripheral base address.
877 * @param speed The speed of the RMII mode.
878 * @param duplex The duplex of the RMII mode.
879 */
ENET_QOS_SetMII(ENET_QOS_Type * base,enet_qos_mii_speed_t speed,enet_qos_mii_duplex_t duplex)880 static inline void ENET_QOS_SetMII(ENET_QOS_Type *base, enet_qos_mii_speed_t speed, enet_qos_mii_duplex_t duplex)
881 {
882 uint32_t reg = base->MAC_CONFIGURATION & ~(ENET_QOS_MAC_CONFIGURATION_DM_MASK | ENET_QOS_MAC_CONFIGURATION_PS_MASK |
883 ENET_QOS_MAC_CONFIGURATION_FES_MASK);
884 reg |= ENET_QOS_MAC_CONFIGURATION_DM(duplex) | (uint32_t)speed;
885
886 base->MAC_CONFIGURATION = reg;
887 }
888
889 /*!
890 * @brief Sets the ENET SMI(serial management interface)- MII management interface.
891 *
892 * @param base ENET peripheral base address.
893 * @param csrClock_Hz CSR clock frequency in HZ
894 */
895 void ENET_QOS_SetSMI(ENET_QOS_Type *base, uint32_t csrClock_Hz);
896
897 /*!
898 * @brief Checks if the SMI is busy.
899 *
900 * @param base ENET peripheral base address.
901 * @return The status of MII Busy status.
902 */
ENET_QOS_IsSMIBusy(ENET_QOS_Type * base)903 static inline bool ENET_QOS_IsSMIBusy(ENET_QOS_Type *base)
904 {
905 return ((base->MAC_MDIO_ADDRESS & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK) != 0U) ? true : false;
906 }
907
908 /*!
909 * @brief Reads data from the PHY register through SMI interface.
910 *
911 * @param base ENET peripheral base address.
912 * @return The data read from PHY
913 */
ENET_QOS_ReadSMIData(ENET_QOS_Type * base)914 static inline uint16_t ENET_QOS_ReadSMIData(ENET_QOS_Type *base)
915 {
916 return (uint16_t)(base->MAC_MDIO_DATA & ENET_QOS_MAC_MDIO_DATA_GD_MASK);
917 }
918
919 /*!
920 * @brief Starts an SMI read command.
921 * It supports MDIO IEEE802.3 Clause 22.
922 * After send command, user needs to check whether the transmission is over
923 * with ENET_QOS_IsSMIBusy().
924 *
925 * @param base ENET peripheral base address.
926 * @param phyAddr The PHY address.
927 * @param phyReg The PHY register.
928 */
929 void ENET_QOS_StartSMIRead(ENET_QOS_Type *base, uint32_t phyAddr, uint32_t phyReg);
930
931 /*!
932 * @brief Starts a SMI write command.
933 * It supports MDIO IEEE802.3 Clause 22.
934 * After send command, user needs to check whether the transmission is over
935 * with ENET_QOS_IsSMIBusy().
936 *
937 * @param base ENET peripheral base address.
938 * @param phyAddr The PHY address.
939 * @param phyReg The PHY register.
940 * @param data The data written to PHY.
941 */
942 void ENET_QOS_StartSMIWrite(ENET_QOS_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
943
944 /*!
945 * @brief Starts a SMI write command.
946 * It supports MDIO IEEE802.3 Clause 45.
947 * After send command, user needs to check whether the transmission is over
948 * with ENET_QOS_IsSMIBusy().
949 *
950 * @param base ENET peripheral base address.
951 * @param phyAddr The PHY address.
952 * @param device The PHY device type.
953 * @param phyReg The PHY register address.
954 * @param data The data written to PHY.
955 */
956 void ENET_QOS_StartExtC45SMIWrite(
957 ENET_QOS_Type *base, uint32_t phyAddr, uint32_t device, uint32_t phyReg, uint32_t data);
958
959 /*!
960 * @brief Starts a SMI read command.
961 * It supports MDIO IEEE802.3 Clause 45.
962 * After send command, user needs to check whether the transmission is over
963 * with ENET_QOS_IsSMIBusy().
964 *
965 * @param base ENET peripheral base address.
966 * @param phyAddr The PHY address.
967 * @param device The PHY device type.
968 * @param phyReg The PHY register address.
969 */
970 void ENET_QOS_StartExtC45SMIRead(ENET_QOS_Type *base, uint32_t phyAddr, uint32_t device, uint32_t phyReg);
971 /* @} */
972
973 /*!
974 * @name Other basic operation
975 * @{
976 */
977
978 /*!
979 * @brief Sets the ENET module Mac address.
980 *
981 * @param base ENET peripheral base address.
982 * @param macAddr The six-byte Mac address pointer.
983 * The pointer is allocated by application and input into the API.
984 * @param index Configure macAddr to MAC_ADDRESS[index] register.
985 */
ENET_QOS_SetMacAddr(ENET_QOS_Type * base,uint8_t * macAddr,uint8_t index)986 static inline void ENET_QOS_SetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index)
987 {
988 uint32_t lowAddress;
989 uint32_t highAddress;
990
991 assert(macAddr != NULL);
992
993 lowAddress = ((uint32_t)macAddr[3] << 24U) | ((uint32_t)macAddr[2] << 16U) | ((uint32_t)macAddr[1] << 8U) |
994 ((uint32_t)macAddr[0]);
995 highAddress = ((uint32_t)macAddr[5] << 8U) | ((uint32_t)macAddr[4]);
996 /* Set Macaddr, the MAC address registers are configured to be double-synchronized to the MII clock
997 domains, then the synchronization is triggered only when bits 31:24 (in little-endian mode)
998 or bits 7:0 (in Big-Endian mode) of the MAC address low register are written to.*/
999 base->MAC_ADDRESS[index].HIGH = highAddress | ENET_QOS_HIGH_AE_MASK;
1000 base->MAC_ADDRESS[index].LOW = lowAddress;
1001 }
1002
1003 /*!
1004 * @brief Gets the ENET module Mac address.
1005 *
1006 * @param base ENET peripheral base address.
1007 * @param macAddr The six-byte Mac address pointer.
1008 * The pointer is allocated by application and input into the API.
1009 * @param index Get macAddr from MAC_ADDRESS[index] register.
1010 */
1011 void ENET_QOS_GetMacAddr(ENET_QOS_Type *base, uint8_t *macAddr, uint8_t index);
1012
1013 /*!
1014 * @brief Adds the ENET_QOS device to a multicast group.
1015 *
1016 * @param base ENET_QOS peripheral base address.
1017 * @param address The six-byte multicast group address which is provided by application.
1018 */
1019 void ENET_QOS_AddMulticastGroup(ENET_QOS_Type *base, uint8_t *address);
1020
1021 /*!
1022 * @brief Moves the ENET_QOS device from a multicast group.
1023 *
1024 * @param base ENET_QOS peripheral base address.
1025 * @param address The six-byte multicast group address which is provided by application.
1026 */
1027 void ENET_QOS_LeaveMulticastGroup(ENET_QOS_Type *base, uint8_t *address);
1028
1029 /*!
1030 * @brief Enable ENET device to accept all multicast frames.
1031 *
1032 * @param base ENET peripheral base address.
1033 */
ENET_QOS_AcceptAllMulticast(ENET_QOS_Type * base)1034 static inline void ENET_QOS_AcceptAllMulticast(ENET_QOS_Type *base)
1035 {
1036 uint32_t reg = base->MAC_PACKET_FILTER;
1037
1038 base->MAC_PACKET_FILTER = reg | ENET_QOS_MAC_PACKET_FILTER_PM_MASK;
1039 }
1040
1041 /*!
1042 * @brief ENET device reject to accept all multicast frames.
1043 *
1044 * @param base ENET peripheral base address.
1045 */
ENET_QOS_RejectAllMulticast(ENET_QOS_Type * base)1046 static inline void ENET_QOS_RejectAllMulticast(ENET_QOS_Type *base)
1047 {
1048 uint32_t reg = base->MAC_PACKET_FILTER;
1049
1050 base->MAC_PACKET_FILTER = reg & ~ENET_QOS_MAC_PACKET_FILTER_PM_MASK;
1051 }
1052
1053 /*!
1054 * @brief Set the MAC to enter into power down mode.
1055 * the remote power wake up frame and magic frame can wake up
1056 * the ENET from the power down mode.
1057 *
1058 * @param base ENET peripheral base address.
1059 * @param wakeFilter The wakeFilter provided to configure the wake up frame filter.
1060 * Set the wakeFilter to NULL is not required. But if you have the filter requirement,
1061 * please make sure the wakeFilter pointer shall be eight continuous
1062 * 32-bits configuration.
1063 */
1064 void ENET_QOS_EnterPowerDown(ENET_QOS_Type *base, uint32_t *wakeFilter);
1065
1066 /*!
1067 * @brief Set the MAC to exit power down mode.
1068 * Exit from the power down mode and recover to normal work mode.
1069 *
1070 * @param base ENET peripheral base address.
1071 */
ENET_QOS_ExitPowerDown(ENET_QOS_Type * base)1072 static inline void ENET_QOS_ExitPowerDown(ENET_QOS_Type *base)
1073 {
1074 /* Clear and status ans reset the power down. */
1075 base->MAC_PMT_CONTROL_STATUS &= ~ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK;
1076
1077 /* Restore the tx which is disabled when enter power down mode. */
1078 base->DMA_CH[0].DMA_CHX_TX_CTRL |= ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK;
1079 base->DMA_CH[1].DMA_CHX_TX_CTRL |= ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK;
1080 base->MAC_CONFIGURATION |= ENET_QOS_MAC_CONFIGURATION_TE_MASK;
1081 }
1082
1083 /*!
1084 * @brief Enable/Disable Rx parser,please notice that for enable/disable Rx Parser,
1085 * should better disable Receive first.
1086 *
1087 * @param base ENET_QOS peripheral base address.
1088 * @param enable Enable/Disable Rx parser function
1089 * @retval kStatus_Success Configure rx parser success.
1090 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1091 */
1092 status_t ENET_QOS_EnableRxParser(ENET_QOS_Type *base, bool enable);
1093 /* @} */
1094
1095 /*!
1096 * @name Interrupts.
1097 * @{
1098 */
1099
1100 /*!
1101 * @brief Enables the ENET DMA and MAC interrupts.
1102 *
1103 * This function enables the ENET interrupt according to the provided mask. The mask
1104 * is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1105 * For example, to enable the dma and mac interrupt, do the following.
1106 * @code
1107 * ENET_QOS_EnableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);
1108 * @endcode
1109 *
1110 * @param base ENET peripheral base address.
1111 * @param mask ENET interrupts to enable. This is a logical OR of both
1112 * enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1113 */
1114 void ENET_QOS_EnableInterrupts(ENET_QOS_Type *base, uint32_t mask);
1115
1116 /*!
1117 * @brief Disables the ENET DMA and MAC interrupts.
1118 *
1119 * This function disables the ENET interrupt according to the provided mask. The mask
1120 * is a logical OR of enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1121 * For example, to disable the dma and mac interrupt, do the following.
1122 * @code
1123 * ENET_QOS_DisableInterrupts(ENET, kENET_QOS_DmaRx | kENET_QOS_DmaTx | kENET_QOS_MacPmt);
1124 * @endcode
1125 *
1126 * @param base ENET peripheral base address.
1127 * @param mask ENET interrupts to disables. This is a logical OR of both
1128 * enumeration :: enet_qos_dma_interrupt_enable_t and enet_qos_mac_interrupt_enable_t.
1129 */
1130 void ENET_QOS_DisableInterrupts(ENET_QOS_Type *base, uint32_t mask);
1131
1132 /*!
1133 * @brief Gets the ENET DMA interrupt status flag.
1134 *
1135 * @param base ENET peripheral base address.
1136 * @param channel The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.
1137 * @return The event status of the interrupt source. This is the logical OR of members
1138 * of the enumeration :: enet_qos_dma_interrupt_enable_t.
1139 */
ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type * base,uint8_t channel)1140 static inline uint32_t ENET_QOS_GetDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel)
1141 {
1142 return base->DMA_CH[channel].DMA_CHX_STAT;
1143 }
1144
1145 /*!
1146 * @brief Clear the ENET DMA interrupt status flag.
1147 *
1148 * @param base ENET peripheral base address.
1149 * @param channel The DMA Channel. Shall not be larger than ENET_QOS_RING_NUM_MAX.
1150 * @param mask The interrupt status to be cleared. This is the logical OR of members
1151 * of the enumeration :: enet_qos_dma_interrupt_enable_t.
1152 */
ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type * base,uint8_t channel,uint32_t mask)1153 static inline void ENET_QOS_ClearDmaInterruptStatus(ENET_QOS_Type *base, uint8_t channel, uint32_t mask)
1154 {
1155 /* Clear the dam interrupt status bit in dma channel interrupt status register. */
1156 base->DMA_CH[channel].DMA_CHX_STAT = mask;
1157 }
1158
1159 /*!
1160 * @brief Gets the ENET MAC interrupt status flag.
1161 *
1162 * @param base ENET peripheral base address.
1163 * @return The event status of the interrupt source.
1164 * Use the enum in enet_qos_mac_interrupt_enable_t and right shift
1165 * ENET_QOS_MACINT_ENUM_OFFSET to mask the returned value to get the
1166 * exact interrupt status.
1167 */
ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type * base)1168 static inline uint32_t ENET_QOS_GetMacInterruptStatus(ENET_QOS_Type *base)
1169 {
1170 return base->MAC_INTERRUPT_STATUS;
1171 }
1172
1173 /*!
1174 * @brief Clears the ENET mac interrupt events status flag.
1175 *
1176 * This function clears enabled ENET interrupts according to the provided mask. The mask
1177 * is a logical OR of enumeration members. See the @ref enet_qos_mac_interrupt_enable_t.
1178 * For example, to clear the TX frame interrupt and RX frame interrupt, do the following.
1179 * @code
1180 * ENET_QOS_ClearMacInterruptStatus(ENET, kENET_QOS_MacPmt);
1181 * @endcode
1182 *
1183 * @param base ENET peripheral base address.
1184 * @param mask ENET interrupt source to be cleared.
1185 * This is the logical OR of members of the enumeration :: enet_qos_mac_interrupt_enable_t.
1186 */
1187 void ENET_QOS_ClearMacInterruptStatus(ENET_QOS_Type *base, uint32_t mask);
1188
1189 /* @} */
1190
1191 /*!
1192 * @name Functional operation.
1193 * @{
1194 */
1195
1196 /*!
1197 * @brief Get the tx descriptor DMA Own flag.
1198 *
1199 * @param txDesc The given tx descriptor.
1200 * @retval True the dma own tx descriptor, false application own tx descriptor.
1201 *
1202 */
ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t * txDesc)1203 static inline bool ENET_QOS_IsTxDescriptorDmaOwn(enet_qos_tx_bd_struct_t *txDesc)
1204 {
1205 return ((txDesc->controlStat & ENET_QOS_TXDESCRIP_RD_OWN_MASK) != 0U) ? true : false;
1206 }
1207
1208 /*!
1209 * @brief Setup a given tx descriptor.
1210 * This function is a low level functional API to setup or prepare
1211 * a given tx descriptor.
1212 *
1213 * @param txDesc The given tx descriptor.
1214 * @param buffer1 The first buffer address in the descriptor.
1215 * @param bytes1 The bytes in the fist buffer.
1216 * @param buffer2 The second buffer address in the descriptor.
1217 * @param bytes2 The bytes in the second buffer.
1218 * @param framelen The length of the frame to be transmitted.
1219 * @param intEnable Interrupt enable flag.
1220 * @param tsEnable The timestamp enable.
1221 * @param flag The flag of this tx descriptor, @ref enet_qos_desc_flag .
1222 * @param slotNum The slot num used for AV only.
1223 *
1224 * @note This must be called after all the ENET initialization.
1225 * And should be called when the ENET receive/transmit is required.
1226 * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
1227 * memory until the packet has been fully transmitted. The buffers
1228 * should be free or requeued in the transmit interrupt irq handler.
1229 */
1230 void ENET_QOS_SetupTxDescriptor(enet_qos_tx_bd_struct_t *txDesc,
1231 void *buffer1,
1232 uint32_t bytes1,
1233 void *buffer2,
1234 uint32_t bytes2,
1235 uint32_t framelen,
1236 bool intEnable,
1237 bool tsEnable,
1238 enet_qos_desc_flag flag,
1239 uint8_t slotNum);
1240
1241 /*!
1242 * @brief Update the tx descriptor tail pointer.
1243 * This function is a low level functional API to update the
1244 * the tx descriptor tail.
1245 * This is called after you setup a new tx descriptor to update
1246 * the tail pointer to make the new descriptor accessible by DMA.
1247 *
1248 * @param base ENET peripheral base address.
1249 * @param channel The tx DMA channel.
1250 * @param txDescTailAddrAlign The new tx tail pointer address.
1251 *
1252 */
ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type * base,uint8_t channel,uint32_t txDescTailAddrAlign)1253 static inline void ENET_QOS_UpdateTxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t txDescTailAddrAlign)
1254 {
1255 base->DMA_CH[channel].DMA_CHX_TXDESC_TAIL_PTR = txDescTailAddrAlign & ~ENET_QOS_ADDR_ALIGNMENT;
1256 }
1257
1258 /*!
1259 * @brief Update the rx descriptor tail pointer.
1260 * This function is a low level functional API to update the
1261 * the rx descriptor tail.
1262 * This is called after you setup a new rx descriptor to update
1263 * the tail pointer to make the new descriptor accessible by DMA
1264 * and to anouse the rx poll command for DMA.
1265 *
1266 * @param base ENET peripheral base address.
1267 * @param channel The rx DMA channel.
1268 * @param rxDescTailAddrAlign The new rx tail pointer address.
1269 *
1270 */
ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type * base,uint8_t channel,uint32_t rxDescTailAddrAlign)1271 static inline void ENET_QOS_UpdateRxDescriptorTail(ENET_QOS_Type *base, uint8_t channel, uint32_t rxDescTailAddrAlign)
1272 {
1273 base->DMA_CH[channel].DMA_CHX_RXDESC_TAIL_PTR = rxDescTailAddrAlign & ~ENET_QOS_ADDR_ALIGNMENT;
1274 }
1275
1276 /*!
1277 * @brief Gets the context in the ENET rx descriptor.
1278 * This function is a low level functional API to get the
1279 * the status flag from a given rx descriptor.
1280 *
1281 * @param rxDesc The given rx descriptor.
1282 * @retval The RDES3 regions for write-back format rx buffer descriptor.
1283 *
1284 * @note This must be called after all the ENET initialization.
1285 * And should be called when the ENET receive/transmit is required.
1286 */
ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t * rxDesc)1287 static inline uint32_t ENET_QOS_GetRxDescriptor(enet_qos_rx_bd_struct_t *rxDesc)
1288 {
1289 assert(rxDesc != NULL);
1290
1291 return rxDesc->control;
1292 }
1293 /*!
1294 * @brief Updates the buffers and the own status for a given rx descriptor.
1295 * This function is a low level functional API to Updates the
1296 * buffers and the own status for a given rx descriptor.
1297 *
1298 * @param rxDesc The given rx descriptor.
1299 * @param buffer1 The first buffer address in the descriptor.
1300 * @param buffer2 The second buffer address in the descriptor.
1301 * @param intEnable Interrupt enable flag.
1302 * @param doubleBuffEnable The double buffer enable flag.
1303 *
1304 * @note This must be called after all the ENET initialization.
1305 * And should be called when the ENET receive/transmit is required.
1306 */
1307 void ENET_QOS_UpdateRxDescriptor(
1308 enet_qos_rx_bd_struct_t *rxDesc, void *buffer1, void *buffer2, bool intEnable, bool doubleBuffEnable);
1309
1310 /*!
1311 * @brief Configure flexible rx parser.
1312 *
1313 * This function is used to configure the flexible rx parser table.
1314 *
1315 * @param base ENET peripheral base address..
1316 * @param rxpConfig The rx parser configuration pointer.
1317 * @param entryCount The rx parser entry count.
1318 * @retval kStatus_Success Configure rx parser success.
1319 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1320 */
1321 status_t ENET_QOS_ConfigureRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryCount);
1322
1323 /*!
1324 * @brief Read flexible rx parser configuration at specified index.
1325 *
1326 * This function is used to read flexible rx parser configuration at specified index.
1327 *
1328 * @param base ENET peripheral base address..
1329 * @param rxpConfig The rx parser configuration pointer.
1330 * @param entryIndex The rx parser entry index to read, start from 0.
1331 * @retval kStatus_Success Configure rx parser success.
1332 * @retval kStatus_ENET_QOS_Timeout Poll status flag timeout.
1333 */
1334 status_t ENET_QOS_ReadRxParser(ENET_QOS_Type *base, enet_qos_rxp_config_t *rxpConfig, uint16_t entryIndex);
1335
1336 /*!
1337 * @brief Program Gate Control List.
1338 *
1339 * This function is used to program the Enhanced Scheduled Transmisson. (IEEE802.1Qbv)
1340 *
1341 * @param base ENET peripheral base address..
1342 * @param gcl Pointer to the Gate Control List structure.
1343 * @param ptpClk_Hz frequency of the PTP clock.
1344 */
1345 status_t ENET_QOS_EstProgramGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t ptpClk_Hz);
1346
1347 /*!
1348 * @brief Read Gate Control List.
1349 *
1350 * This function is used to read the Enhanced Scheduled Transmisson list. (IEEE802.1Qbv)
1351 *
1352 * @param base ENET peripheral base address..
1353 * @param gcl Pointer to the Gate Control List structure.
1354 * @param listLen length of the provided opList array in gcl structure.
1355 * @param hwList Boolean if True read HW list, false read SW list.
1356 */
1357 status_t ENET_QOS_EstReadGcl(ENET_QOS_Type *base, enet_qos_est_gcl_t *gcl, uint32_t listLen, bool hwList);
1358
1359 /*!
1360 * @brief Enable Frame Preemption.
1361 *
1362 * This function is used to enable frame preemption. (IEEE802.1Qbu)
1363 *
1364 * @param base ENET peripheral base address..
1365 */
ENET_QOS_FpeEnable(ENET_QOS_Type * base)1366 static inline void ENET_QOS_FpeEnable(ENET_QOS_Type *base)
1367 {
1368 base->MAC_FPE_CTRL_STS |= ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK;
1369 }
1370
1371 /*!
1372 * @brief Disable Frame Preemption.
1373 *
1374 * This function is used to disable frame preemption. (IEEE802.1Qbu)
1375 *
1376 * @param base ENET peripheral base address..
1377 */
ENET_QOS_FpeDisable(ENET_QOS_Type * base)1378 static inline void ENET_QOS_FpeDisable(ENET_QOS_Type *base)
1379 {
1380 base->MAC_FPE_CTRL_STS &= ~ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK;
1381 }
1382
1383 /*!
1384 * @brief Configure preemptable transmit queues.
1385 *
1386 * This function is used to configure the preemptable queues. (IEEE802.1Qbu)
1387 *
1388 * @param base ENET peripheral base address..
1389 * @param queueMask bitmask representing queues to set in preemptable mode.
1390 * The N-th bit represents the queue N.
1391 */
ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type * base,uint8_t queueMask)1392 static inline void ENET_QOS_FpeConfigPreemptable(ENET_QOS_Type *base, uint8_t queueMask)
1393 {
1394 uint32_t control;
1395
1396 control = base->MTL_FPE_CTRL_STS & ~ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK;
1397 control |= ENET_QOS_MTL_FPE_CTRL_STS_PEC(queueMask);
1398 base->MTL_FPE_CTRL_STS = control;
1399 }
1400
1401 /*!
1402 * @brief Sets the ENET AVB feature.
1403 *
1404 * ENET_QOS AVB feature configuration, set transmit bandwidth.
1405 * This API is called when the AVB feature is required.
1406 *
1407 * @param base ENET_QOS peripheral base address.
1408 * @param config The ENET_QOS AVB feature configuration structure.
1409 * @param queueIndex ENET_QOS queue index.
1410 */
1411 void ENET_QOS_AVBConfigure(ENET_QOS_Type *base, const enet_qos_cbs_config_t *config, uint8_t queueIndex);
1412
1413 /*!
1414 * @brief Gets statistical data in transfer.
1415 *
1416 * @param base ENET_QOS peripheral base address.
1417 * @param statistics The statistics structure pointer.
1418 */
1419 void ENET_QOS_GetStatistics(ENET_QOS_Type *base, enet_qos_transfer_stats_t *statistics);
1420
1421 /* @} */
1422
1423 /*!
1424 * @name Transactional operation
1425 * @{
1426 */
1427
1428 /*!
1429 * @brief Create ENET Handler
1430 *
1431 * This is a transactional API and it's provided to store all data which are needed
1432 * during the whole transactional process. This API should not be used when you use
1433 * functional APIs to do data tx/rx. This is function will store many data/flag for
1434 * transactional use, so all configure API such as ENET_QOS_Init(), ENET_QOS_DescriptorInit(),
1435 * ENET_QOS_EnableInterrupts() etc.
1436 *
1437 * @note as our transactional transmit API use the zero-copy transmit buffer.
1438 * so there are two thing we emphasize here:
1439 * 1. tx buffer free/requeue for application should be done in the tx
1440 * interrupt handler. Please set callback: kENET_QOS_TxIntEvent with tx buffer free/requeue
1441 * process APIs.
1442 * 2. the tx interrupt is forced to open.
1443 *
1444 * @param base ENET peripheral base address.
1445 * @param handle ENET handler.
1446 * @param config ENET configuration.
1447 * @param bufferConfig ENET buffer configuration.
1448 * @param callback The callback function.
1449 * @param userData The application data.
1450 */
1451 void ENET_QOS_CreateHandler(ENET_QOS_Type *base,
1452 enet_qos_handle_t *handle,
1453 enet_qos_config_t *config,
1454 enet_qos_buffer_config_t *bufferConfig,
1455 enet_qos_callback_t callback,
1456 void *userData);
1457
1458 /*!
1459 * @brief Gets the size of the read frame.
1460 * This function gets a received frame size from the ENET buffer descriptors.
1461 * @note The FCS of the frame is automatically removed by MAC and the size is the length without the FCS.
1462 * After calling @ref ENET_QOS_GetRxFrameSize, @ref ENET_QOS_ReadFrame() should be called to update the
1463 * receive buffers If the result is not "kStatus_ENET_QOS_RxFrameEmpty".
1464 *
1465 * @param base ENET peripheral base address.
1466 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
1467 * @param length The length of the valid frame received.
1468 * @param channel The DMAC channel for the rx.
1469 * @retval kStatus_ENET_QOS_RxFrameEmpty No frame received. Should not call ENET_QOS_ReadFrame to read frame.
1470 * @retval kStatus_ENET_QOS_RxFrameError Data error happens. @ref ENET_QOS_ReadFrame should be called with NULL data
1471 * and NULL length to update the receive buffers.
1472 * @retval kStatus_Success Receive a frame Successfully then the @ref ENET_QOS_ReadFrame
1473 * should be called with the right data buffer and the captured data length input.
1474 */
1475 status_t ENET_QOS_GetRxFrameSize(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint32_t *length, uint8_t channel);
1476
1477 /*!
1478 * @brief Reads a frame from the ENET device.
1479 * This function reads a frame from the ENET DMA descriptors.
1480 * The ENET_QOS_GetRxFrameSize should be used to get the size of the prepared data buffer.
1481 * For example use rx dma channel 0:
1482 * @code
1483 * uint32_t length;
1484 * enet_qos_handle_t g_handle;
1485 * status = ENET_QOS_GetRxFrameSize(&g_handle, &length, 0);
1486 * if (length != 0)
1487 * {
1488 * uint8_t *data = memory allocate interface;
1489 * if (!data)
1490 * {
1491 * ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
1492 * }
1493 * else
1494 * {
1495 * status = ENET_QOS_ReadFrame(ENET, &g_handle, data, length, 0);
1496 * }
1497 * }
1498 * else if (status == kStatus_ENET_QOS_RxFrameError)
1499 * {
1500 * ENET_QOS_ReadFrame(ENET, &g_handle, NULL, 0, 0);
1501 * }
1502 * @endcode
1503 * @param base ENET peripheral base address.
1504 * @param handle The ENET handler structure. This is the same handler pointer used in the ENET_QOS_Init.
1505 * @param data The data buffer provided by user to store the frame which memory size should be at least "length".
1506 * @param length The size of the data buffer which is still the length of the received frame.
1507 * @param channel The rx DMA channel. shall not be larger than 2.
1508 * @param ts Pointer to the structure @ref enet_qos_ptp_time_t to save frame timestamp.
1509 * @return The execute status, successful or failure.
1510 */
1511 status_t ENET_QOS_ReadFrame(ENET_QOS_Type *base,
1512 enet_qos_handle_t *handle,
1513 uint8_t *data,
1514 uint32_t length,
1515 uint8_t channel,
1516 enet_qos_ptp_time_t *ts);
1517
1518 /*!
1519 * @brief Transmits an ENET frame.
1520 * @note The CRC is automatically appended to the data. Input the data
1521 * to send without the CRC.
1522 *
1523 * @param base ENET peripheral base address.
1524 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
1525 * @param data The data buffer provided by user to be send.
1526 * @param length The length of the data to be send.
1527 * @param channel Channel to send the frame, same with queue index.
1528 * @param isNeedTs True to enable timestamp save for the frame
1529 * @param context pointer to user context to be kept in the tx dirty frame information.
1530 * @retval kStatus_Success Send frame succeed.
1531 * @retval kStatus_ENET_QOS_TxFrameBusy Transmit buffer descriptor is busy under transmission.
1532 * The transmit busy happens when the data send rate is over the MAC capacity.
1533 * The waiting mechanism is recommended to be added after each call return with
1534 * kStatus_ENET_QOS_TxFrameBusy.
1535 */
1536 status_t ENET_QOS_SendFrame(ENET_QOS_Type *base,
1537 enet_qos_handle_t *handle,
1538 uint8_t *data,
1539 uint32_t length,
1540 uint8_t channel,
1541 bool isNeedTs,
1542 void *context);
1543
1544 /*!
1545 * @brief Reclaim tx descriptors.
1546 * This function is used to update the tx descriptor status and
1547 * store the tx timestamp when the 1588 feature is enabled.
1548 * This is called by the transmit interrupt IRQ handler after the
1549 * complete of a frame transmission.
1550 *
1551 * @param base ENET peripheral base address.
1552 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_QOS_Init.
1553 * @param channel The tx DMA channel.
1554 *
1555 */
1556 void ENET_QOS_ReclaimTxDescriptor(ENET_QOS_Type *base, enet_qos_handle_t *handle, uint8_t channel);
1557
1558 /*!
1559 * @brief The ENET IRQ handler.
1560 *
1561 * @param base ENET peripheral base address.
1562 * @param handle The ENET handler pointer.
1563 */
1564 void ENET_QOS_CommonIRQHandler(ENET_QOS_Type *base, enet_qos_handle_t *handle);
1565
1566 /*!
1567 * @brief Set the second level IRQ handler, allow user to overwrite the default
1568 * second level weak IRQ handler.
1569 *
1570 * @param base ENET peripheral base address.
1571 * @param ISRHandler The handler to install.
1572 */
1573 void ENET_QOS_SetISRHandler(ENET_QOS_Type *base, enet_qos_isr_t ISRHandler);
1574
1575 /* @} */
1576 /*!
1577 * @name ENET Enhanced function operation
1578 * @{
1579 */
1580
1581 /*!
1582 * @brief Correct the ENET PTP 1588 timer in coarse method.
1583 *
1584 * @param base ENET peripheral base address.
1585 * @param operation The system time operation, refer to "enet_qos_systime_op"
1586 * @param second The correction second.
1587 * @param nanosecond The correction nanosecond.
1588 */
1589 status_t ENET_QOS_Ptp1588CorrectTimerInCoarse(ENET_QOS_Type *base,
1590 enet_qos_systime_op operation,
1591 uint32_t second,
1592 uint32_t nanosecond);
1593
1594 /*!
1595 * @brief Correct the ENET PTP 1588 timer in fine method.
1596 *
1597 *
1598 * @param base ENET peripheral base address.
1599 * @param addend The addend value to be set in the fine method
1600 * @note Should take refer to the chapter "System time correction" and
1601 * see the description for the "fine correction method".
1602 */
1603 status_t ENET_QOS_Ptp1588CorrectTimerInFine(ENET_QOS_Type *base, uint32_t addend);
1604
1605 /*!
1606 * @brief Get the ENET Time stamp current addend value.
1607 *
1608 * @param base ENET peripheral base address.
1609 * @return The addend value.
1610 */
ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type * base)1611 static inline uint32_t ENET_QOS_Ptp1588GetAddend(ENET_QOS_Type *base)
1612 {
1613 return base->MAC_TIMESTAMP_ADDEND;
1614 }
1615
1616 /*!
1617 * @brief Gets the current ENET time from the PTP 1588 timer without IRQ disable.
1618 *
1619 * @param base ENET peripheral base address.
1620 * @param second The PTP 1588 system timer second.
1621 * @param nanosecond The PTP 1588 system timer nanosecond.
1622 * For the unit of the nanosecond is 1ns. so the nanosecond is the real nanosecond.
1623 */
1624 void ENET_QOS_Ptp1588GetTimerNoIRQDisable(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond);
1625
1626 /*!
1627 * @brief Sets the ENET PTP 1588 PPS control.
1628 * All channels operate in flexible PPS output mode.
1629 *
1630 * @param base ENET peripheral base address.
1631 * @param instance The ENET QOS PTP PPS instance.
1632 * @param trgtMode The target time register mode.
1633 * @param cmd The target flexible PPS output control command.
1634 */
ENET_Ptp1588PpsControl(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,enet_qos_ptp_pps_trgt_mode_t trgtMode,enet_qos_ptp_pps_cmd_t cmd)1635 static inline status_t ENET_Ptp1588PpsControl(ENET_QOS_Type *base,
1636 enet_qos_ptp_pps_instance_t instance,
1637 enet_qos_ptp_pps_trgt_mode_t trgtMode,
1638 enet_qos_ptp_pps_cmd_t cmd)
1639 {
1640 uint32_t reg = 0UL;
1641 uint8_t shift = (uint8_t)instance * 8U;
1642 uint32_t pps_config = ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0((uint32_t)trgtMode) |
1643 ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD((uint32_t)cmd);
1644
1645 reg = base->MAC_PPS_CONTROL;
1646
1647 /* Make sure CMD field is all zero */
1648 if ((reg & (0xFUL << shift)) != 0UL)
1649 {
1650 return kStatus_ENET_QOS_PpsBusy;
1651 }
1652
1653 reg &= ~(0xFFUL << shift);
1654 reg |= (pps_config << shift) | ENET_QOS_MAC_PPS_CONTROL_PPSEN0(1U);
1655
1656 base->MAC_PPS_CONTROL = reg;
1657
1658 return kStatus_Success;
1659 }
1660
1661 /*!
1662 * @brief Sets the ENET OQS PTP 1588 PPS target time registers.
1663 *
1664 * @param base ENET QOS peripheral base address.
1665 * @param instance The ENET QOS PTP PPS instance.
1666 * @param seconds The target seconds.
1667 * @param nanoseconds The target nanoseconds.
1668 */
1669 status_t ENET_QOS_Ptp1588PpsSetTrgtTime(ENET_QOS_Type *base,
1670 enet_qos_ptp_pps_instance_t instance,
1671 uint32_t seconds,
1672 uint32_t nanoseconds);
1673
1674 /*!
1675 * @brief Sets the ENET OQS PTP 1588 PPS output signal interval
1676 *
1677 * @param base ENET QOS peripheral base address.
1678 * @param instance The ENET QOS PTP PPS instance.
1679 * @param width Signal Width. It is stored in terms of number of
1680 * units of sub-second increment value. The width value must be
1681 * lesser than interval value.
1682 */
ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,uint32_t width)1683 static inline void ENET_QOS_Ptp1588PpsSetWidth(ENET_QOS_Type *base,
1684 enet_qos_ptp_pps_instance_t instance,
1685 uint32_t width)
1686 {
1687 uint32_t *mac_pps_width;
1688
1689 mac_pps_width = (uint32_t *)((uint32_t)&base->MAC_PPS0_WIDTH + 0x10U * (uint32_t)instance);
1690
1691 *mac_pps_width = ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(width);
1692 }
1693
1694 /*!
1695 * @brief Sets the ENET OQS PTP 1588 PPS output signal width
1696 *
1697 * @param base ENET QOS peripheral base address.
1698 * @param instance The ENET QOS PTP PPS instance.
1699 * @param interval Signal Interval. It is stored in terms of number of
1700 * units of sub-second increment value.
1701 */
ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type * base,enet_qos_ptp_pps_instance_t instance,uint32_t interval)1702 static inline void ENET_QOS_Ptp1588PpsSetInterval(ENET_QOS_Type *base,
1703 enet_qos_ptp_pps_instance_t instance,
1704 uint32_t interval)
1705 {
1706 uint32_t *mac_pps_interval;
1707
1708 mac_pps_interval = (uint32_t *)((uint32_t)&base->MAC_PPS0_INTERVAL + 0x10U * (uint32_t)instance);
1709
1710 *mac_pps_interval = ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(interval);
1711 }
1712
1713 /*!
1714 * @brief Gets the current ENET time from the PTP 1588 timer.
1715 *
1716 * @param base ENET peripheral base address.
1717 * @param second The PTP 1588 system timer second.
1718 * @param nanosecond The PTP 1588 system timer nanosecond.
1719 * For the unit of the nanosecond is 1ns.so the nanosecond is the real nanosecond.
1720 */
1721 void ENET_QOS_Ptp1588GetTimer(ENET_QOS_Type *base, uint64_t *second, uint32_t *nanosecond);
1722
1723 /*!
1724 * @brief Gets the time stamp of the transmit frame.
1725 *
1726 * This function is used for PTP stack to get the timestamp captured by the ENET driver.
1727 *
1728 * @param handle The ENET handler pointer.This is the same state pointer used in
1729 * ENET_QOS_Init.
1730 * @param txFrame Input parameter, pointer to @ref enet_qos_frame_info_t for saving read out frame information.
1731 * @param channel Channel for searching the tx frame.
1732 */
1733 void ENET_QOS_GetTxFrame(enet_qos_handle_t *handle, enet_qos_frame_info_t *txFrame, uint8_t channel);
1734
1735 /*!
1736 * @brief Receives one frame in specified BD ring with zero copy.
1737 *
1738 * This function will use the user-defined allocate and free callback. Every time application gets one frame through
1739 * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.
1740 * @note This function will drop current frame and update related BDs as available for DMA if new buffers allocating
1741 * fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer)
1742 * to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this
1743 * function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's
1744 * always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according
1745 * to specific design in this case.
1746 *
1747 * @param base ENET peripheral base address.
1748 * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
1749 * @param rxFrame The received frame information structure provided by user.
1750 * @param channel Channel for searching the rx frame.
1751 * @retval kStatus_Success Succeed to get one frame and allocate new memory for Rx buffer.
1752 * @retval kStatus_ENET_QOS_RxFrameEmpty There's no Rx frame in the BD.
1753 * @retval kStatus_ENET_QOS_RxFrameError There's issue in this receiving.
1754 * @retval kStatus_ENET_QOS_RxFrameDrop There's no new buffer memory for BD, drop this frame.
1755 */
1756 status_t ENET_QOS_GetRxFrame(ENET_QOS_Type *base,
1757 enet_qos_handle_t *handle,
1758 enet_qos_rx_frame_struct_t *rxFrame,
1759 uint8_t channel);
1760 /* @} */
1761
1762 #if defined(__cplusplus)
1763 }
1764 #endif
1765
1766 /*! @}*/
1767
1768 #endif /* _FSL_ENET_QOS_H_ */
1769
