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Searched refs:DMAMUX_CHCFG_ENBL_MASK (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_dmamux.h79 base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_EnableChannel()
96 base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_DisableChannel()
98 base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_DisableChannel()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_dmamux.h79 base->CHCFG[channel] |= DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_EnableChannel()
96 base->CHCFG[channel] &= ~DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_DisableChannel()
98 base->CHCFG[channel] &= ~(uint8_t)DMAMUX_CHCFG_ENBL_MASK; in DMAMUX_DisableChannel()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h1030 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
1032 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h3411 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
3417 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h2513 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
2515 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h4109 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
4115 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h2513 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
2515 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h4913 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
4919 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h4918 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
4924 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h2170 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
2172 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h9666 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
9673 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h1887 #define DMAMUX_CHCFG_ENBL_MASK 0x80u macro
1890 …) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h2099 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
2101 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h2170 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
2172 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h1887 #define DMAMUX_CHCFG_ENBL_MASK 0x80u macro
1890 …) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h1887 #define DMAMUX_CHCFG_ENBL_MASK 0x80u macro
1890 …) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_ENBL_SHIFT))&DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h9621 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
9627 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h8695 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
8701 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h9625 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
9631 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h8689 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
8695 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h9515 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) macro
9521 … (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h10226 #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) macro
10232 … (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h12235 #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) macro
12241 … (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h15577 #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) macro
15583 … (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h15559 #define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) macro
15565 … (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)

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