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Searched refs:DMA2_IRQn (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h138 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
993 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h153 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ enumerator
3314 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h146 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
2475 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-2.7.6/mcux/devices/MKE14F16/
DMKE14F16.h128 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
4005 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h146 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
2475 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-2.7.6/mcux/devices/MKE16F16/
DMKE16F16.h128 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
4808 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-2.7.6/mcux/devices/MKE18F16/
DMKE18F16.h128 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
4812 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h101 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
2133 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h160 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ enumerator
9554 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h118 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
1784 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h100 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
2062 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h101 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
2133 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h118 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
1784 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h118 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
1784 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
/hal_nxp-2.7.6/mcux/devices/MIMXRT1011/
DMIMXRT1011.h88 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ enumerator
10173 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DM…