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Searched refs:DMA (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_dma.h259 base->DMA[channel].SAR = srcAddr; in DMA_SetSourceAddress()
273 base->DMA[channel].DAR = destAddr; in DMA_SetDestinationAddress()
287 base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(size); in DMA_SetTransferSize()
318 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_CS_MASK)) | DMA_DCR_CS(enable); in DMA_EnableCycleSteal()
335 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_AA_MASK)) | DMA_DCR_AA(enable); in DMA_EnableAutoAlign()
352 …base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_EADREQ_MASK)) | DMA_DCR_EADREQ(enable… in DMA_EnableAsyncRequest()
365 base->DMA[channel].DCR |= DMA_DCR_EINT(true); in DMA_EnableInterrupts()
378 base->DMA[channel].DCR &= ~DMA_DCR_EINT_MASK; in DMA_DisableInterrupts()
397 base->DMA[channel].DCR |= DMA_DCR_ERQ_MASK; in DMA_EnableChannelRequest()
410 base->DMA[channel].DCR &= ~DMA_DCR_ERQ_MASK; in DMA_DisableChannelRequest()
[all …]
Dfsl_dma.c106 base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); in DMA_ResetChannel()
108 base->DMA[channel].SAR = 0; in DMA_ResetChannel()
109 base->DMA[channel].DAR = 0; in DMA_ResetChannel()
110 base->DMA[channel].DSR_BCR = 0; in DMA_ResetChannel()
112 base->DMA[channel].DCR = DMA_DCR_D_REQ(true) | DMA_DCR_CS(true); in DMA_ResetChannel()
123 base->DMA[channel].SAR = config->srcAddr; in DMA_SetTransferConfig()
125 base->DMA[channel].DAR = config->destAddr; in DMA_SetTransferConfig()
127 base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(config->transferSize); in DMA_SetTransferConfig()
129 tmpreg = base->DMA[channel].DCR; in DMA_SetTransferConfig()
133 base->DMA[channel].DCR = tmpreg; in DMA_SetTransferConfig()
[all …]
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_qtmr.c318 base->CHANNEL[channel].DMA &= ~(uint16_t)TMR_DMA_IEFDE_MASK; in QTMR_EnableInterrupts()
562 reg = base->CHANNEL[channel].DMA; in QTMR_EnableDma()
580 base->CHANNEL[channel].DMA = reg; in QTMR_EnableDma()
595 reg = base->CHANNEL[channel].DMA; in QTMR_DisableDma()
611 base->CHANNEL[channel].DMA = reg; in QTMR_DisableDma()
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h918 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
943 #define CMT_DMA_REG(base) ((base)->DMA)
1624 } DMA[4]; member
1638 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
1640 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
1642 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
1644 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
1646 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h918 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
943 #define CMT_DMA_REG(base) ((base)->DMA)
1624 } DMA[4]; member
1638 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
1640 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
1642 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
1644 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
1646 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h918 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
943 #define CMT_DMA_REG(base) ((base)->DMA)
1624 } DMA[4]; member
1638 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
1640 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
1642 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
1644 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
1646 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h867 } DMA[4]; member
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1298 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1298 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1112 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6813 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h1041 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1112 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h5035 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h5029 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5845 …__IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1015/
DMIMXRT1015.h27741 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h37041 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h37023 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h33844 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h42411 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h36252 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h45070 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1064/
DMIMXRT1064.h44996 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1176/
DMIMXRT1176_cm7.h91903 …__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array off… member

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