Home
last modified time | relevance | path

Searched refs:CR1 (Results 1 – 25 of 30) sorted by relevance

12

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.h158 base->CR1 |= CMP_CR1_EN_MASK; in CMP_Enable()
162 base->CR1 &= ~(uint8_t)CMP_CR1_EN_MASK; in CMP_Enable()
229 base->CR1 |= CMP_CR1_WE_MASK; in CMP_EnableWindowMode()
233 base->CR1 &= (uint8_t)(~CMP_CR1_WE_MASK); in CMP_EnableWindowMode()
Dfsl_cmp.c84 …tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_… in CMP_Init()
111 base->CR1 = tmp8; in CMP_Init()
242 base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ in CMP_SetFilterConfig()
246 base->CR1 &= (uint8_t)(~CMP_CR1_SE_MASK); /* Choose the internal divided bus clock. */ in CMP_SetFilterConfig()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.h158 base->CR1 |= CMP_CR1_EN_MASK; in CMP_Enable()
162 base->CR1 &= ~(uint8_t)CMP_CR1_EN_MASK; in CMP_Enable()
229 base->CR1 |= CMP_CR1_WE_MASK; in CMP_EnableWindowMode()
233 base->CR1 &= (uint8_t)(~CMP_CR1_WE_MASK); in CMP_EnableWindowMode()
Dfsl_cmp.c84 …tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_… in CMP_Init()
111 base->CR1 = tmp8; in CMP_Init()
242 base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ in CMP_SetFilterConfig()
246 base->CR1 &= (uint8_t)(~CMP_CR1_SE_MASK); /* Choose the internal divided bus clock. */ in CMP_SetFilterConfig()
Dfsl_csi.h29 #define CSI_REG_CR1(base) (base)->CR1
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h604 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h711 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
730 #define CMP_CR1_REG(base) ((base)->CR1)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h711 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
730 #define CMP_CR1_REG(base) ((base)->CR1)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h711 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
730 #define CMP_CR1_REG(base) ((base)->CR1)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h866 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1155 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1155 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h970 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6528 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h899 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h970 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h5926 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4784 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h5930 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4778 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5579 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8714 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8696 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8540 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9752 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member

12