| /hal_nxp-2.7.6/mcux/drivers/kinetis/ |
| D | fsl_cmp.c | 114 tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK; in CMP_Init()
116 base->CR0 = tmp8; in CMP_Init()
250 tmp8 = (uint8_t)(base->CR0 & ~CMP_CR0_FILTER_CNT_MASK); in CMP_SetFilterConfig()
252 base->CR0 = tmp8; in CMP_SetFilterConfig()
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| /hal_nxp-2.7.6/mcux/drivers/imx/ |
| D | fsl_cmp.c | 114 tmp8 = base->CR0 & ~(uint8_t)CMP_CR0_HYSTCTR_MASK; in CMP_Init()
116 base->CR0 = tmp8; in CMP_Init()
250 tmp8 = (uint8_t)(base->CR0 & ~CMP_CR0_FILTER_CNT_MASK); in CMP_SetFilterConfig()
252 base->CR0 = tmp8; in CMP_SetFilterConfig()
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| /hal_nxp-2.7.6/mcux/devices/MKL25Z4/ |
| D | MKL25Z4.h | 603 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
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| /hal_nxp-2.7.6/mcux/devices/MKW40Z4/ |
| D | MKW40Z4.h | 710 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
729 #define CMP_CR0_REG(base) ((base)->CR0)
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| /hal_nxp-2.7.6/mcux/devices/MKW20Z4/ |
| D | MKW20Z4.h | 710 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
729 #define CMP_CR0_REG(base) ((base)->CR0)
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| /hal_nxp-2.7.6/mcux/devices/MKW30Z4/ |
| D | MKW30Z4.h | 710 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
729 #define CMP_CR0_REG(base) ((base)->CR0)
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| /hal_nxp-2.7.6/mcux/devices/MK22F51212/ |
| D | MK22F51212.h | 865 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW24D5/ |
| D | MKW24D5.h | 1154 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW22D5/ |
| D | MKW22D5.h | 1154 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW31Z4/ |
| D | MKW31Z4.h | 969 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MK64F12/ |
| D | MK64F12.h | 6527 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW21Z4/ |
| D | MKW21Z4.h | 898 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW41Z4/ |
| D | MKW41Z4.h | 969 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKV56F24/ |
| D | MKV56F24.h | 5925 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MK80F25615/ |
| D | MK80F25615.h | 4783 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKV58F24/ |
| D | MKV58F24.h | 5929 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MK82F25615/ |
| D | MK82F25615.h | 4777 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MK66F18/ |
| D | MK66F18.h | 5578 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 8713 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 8695 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 8539 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 9751 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 9728 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 11089 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 11037 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ member
|
