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Searched refs:CMP_SCR_CFR_MASK (Results 1 – 25 of 28) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c212 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_EnableDMA()
292 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_EnableInterrupts()
313 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_DisableInterrupts()
337 if (0U != (CMP_SCR_CFR_MASK & base->SCR)) in CMP_GetStatusFlags()
360 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_ClearStatusFlags()
364 tmp8 |= CMP_SCR_CFR_MASK; in CMP_ClearStatusFlags()
Dfsl_cmp.h43 …kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occ…
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c212 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_EnableDMA()
292 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_EnableInterrupts()
313 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_DisableInterrupts()
337 if (0U != (CMP_SCR_CFR_MASK & base->SCR)) in CMP_GetStatusFlags()
360 …uint8_t tmp8 = (uint8_t)(base->SCR & ~(CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK)); /* To avoid change t… in CMP_ClearStatusFlags()
364 tmp8 |= CMP_SCR_CFR_MASK; in CMP_ClearStatusFlags()
Dfsl_cmp.h43 …kCMP_OutputRisingEventFlag = CMP_SCR_CFR_MASK, /*!< Rising-edge on the comparison output has occ…
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h666 #define CMP_SCR_CFR_MASK (0x4U) macro
668 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h987 #define CMP_SCR_CFR_MASK (0x4U) macro
993 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1214 #define CMP_SCR_CFR_MASK (0x4U) macro
1216 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1214 #define CMP_SCR_CFR_MASK (0x4U) macro
1216 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4_extension.h2384 #define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_S…
2400 #define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
2404 #define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_S…
2424 …e, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF…
2444 …e, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER…
2464 … value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMA…
DMKW40Z4.h806 #define CMP_SCR_CFR_MASK 0x4u macro
809 …_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1032 #define CMP_SCR_CFR_MASK (0x4U) macro
1034 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6661 #define CMP_SCR_CFR_MASK (0x4U) macro
6667 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h961 #define CMP_SCR_CFR_MASK (0x4U) macro
963 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1032 #define CMP_SCR_CFR_MASK (0x4U) macro
1034 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h806 #define CMP_SCR_CFR_MASK 0x4u macro
809 …_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h806 #define CMP_SCR_CFR_MASK 0x4u macro
809 …_CFR(x) (((uint8_t)(((uint8_t)(x))<<CMP_SCR_CFR_SHIFT))&CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h6047 #define CMP_SCR_CFR_MASK (0x4U) macro
6053 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4905 #define CMP_SCR_CFR_MASK (0x4U) macro
4911 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h6051 #define CMP_SCR_CFR_MASK (0x4U) macro
6057 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4899 #define CMP_SCR_CFR_MASK (0x4U) macro
4905 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5700 #define CMP_SCR_CFR_MASK (0x4U) macro
5706 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8847 #define CMP_SCR_CFR_MASK (0x4U) macro
8853 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8829 #define CMP_SCR_CFR_MASK (0x4U) macro
8835 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8660 #define CMP_SCR_CFR_MASK (0x4U) macro
8666 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9885 #define CMP_SCR_CFR_MASK (0x4U) macro
9891 …(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)

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