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Searched refs:CMP_MUXCR_MSEL_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c193 tmp8 &= ~(uint8_t)(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); in CMP_SetInputChannels()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c193 tmp8 &= ~(uint8_t)(CMP_MUXCR_PSEL_MASK | CMP_MUXCR_MSEL_MASK); in CMP_SetInputChannels()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h691 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
693 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h1040 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
1052 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1239 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
1241 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1239 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
1241 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1057 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
1059 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6723 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
6735 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h836 #define CMP_MUXCR_MSEL_MASK 0x7u macro
839 …L(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
DMKW40Z4_extension.h2591 #define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIF…
2595 #define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(val…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h986 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
988 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1057 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
1059 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h836 #define CMP_MUXCR_MSEL_MASK 0x7u macro
839 …L(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h836 #define CMP_MUXCR_MSEL_MASK 0x7u macro
839 …L(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h6100 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
6112 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4958 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
4970 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h6104 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
6116 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4952 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
4964 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5753 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
5765 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8909 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
8921 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8891 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
8903 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8715 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
8727 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9947 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
9959 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h9904 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
9916 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h11285 #define CMP_MUXCR_MSEL_MASK (0x7U) macro
11297 … (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)

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