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Searched refs:CMP_DACCR_VRSEL_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c277 tmp8 |= CMP_DACCR_VRSEL_MASK; in CMP_SetDACConfig()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c277 tmp8 |= CMP_DACCR_VRSEL_MASK; in CMP_SetDACConfig()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h683 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
685 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h1022 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
1028 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1231 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
1233 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1231 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
1233 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1049 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
1051 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6703 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
6709 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h827 #define CMP_DACCR_VRSEL_MASK 0x40u macro
830 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
DMKW40Z4_extension.h2518 #define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_S…
2522 #define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h978 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
980 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1049 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
1051 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h827 #define CMP_DACCR_VRSEL_MASK 0x40u macro
830 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h827 #define CMP_DACCR_VRSEL_MASK 0x40u macro
830 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VRSEL_SHIFT))&CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h6082 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
6088 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4940 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
4946 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h6086 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
6092 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4934 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
4940 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5735 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
5741 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8889 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
8895 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8871 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
8877 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8697 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
8703 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9927 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
9933 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h9886 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
9892 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h11265 #define CMP_DACCR_VRSEL_MASK (0x40U) macro
11271 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)

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