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Searched refs:CMP_DACCR_DACEN_MASK (Results 1 – 25 of 26) sorted by relevance

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/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c274 tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ in CMP_SetDACConfig()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c274 tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */ in CMP_SetDACConfig()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h686 #define CMP_DACCR_DACEN_MASK (0x80U) macro
688 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h1029 #define CMP_DACCR_DACEN_MASK (0x80U) macro
1035 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1234 #define CMP_DACCR_DACEN_MASK (0x80U) macro
1236 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1234 #define CMP_DACCR_DACEN_MASK (0x80U) macro
1236 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1052 #define CMP_DACCR_DACEN_MASK (0x80U) macro
1054 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6711 #define CMP_DACCR_DACEN_MASK (0x80U) macro
6717 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h831 #define CMP_DACCR_DACEN_MASK 0x80u macro
834 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
DMKW40Z4_extension.h2538 #define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_S…
2542 #define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(…
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h981 #define CMP_DACCR_DACEN_MASK (0x80U) macro
983 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1052 #define CMP_DACCR_DACEN_MASK (0x80U) macro
1054 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h831 #define CMP_DACCR_DACEN_MASK 0x80u macro
834 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h831 #define CMP_DACCR_DACEN_MASK 0x80u macro
834 …(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_DACEN_SHIFT))&CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h6089 #define CMP_DACCR_DACEN_MASK (0x80U) macro
6095 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4947 #define CMP_DACCR_DACEN_MASK (0x80U) macro
4953 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h6093 #define CMP_DACCR_DACEN_MASK (0x80U) macro
6099 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4941 #define CMP_DACCR_DACEN_MASK (0x80U) macro
4947 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5742 #define CMP_DACCR_DACEN_MASK (0x80U) macro
5748 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8897 #define CMP_DACCR_DACEN_MASK (0x80U) macro
8903 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8879 #define CMP_DACCR_DACEN_MASK (0x80U) macro
8885 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8704 #define CMP_DACCR_DACEN_MASK (0x80U) macro
8710 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9935 #define CMP_DACCR_DACEN_MASK (0x80U) macro
9941 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h9893 #define CMP_DACCR_DACEN_MASK (0x80U) macro
9899 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h11273 #define CMP_DACCR_DACEN_MASK (0x80U) macro
11279 … (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)

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