Home
last modified time | relevance | path

Searched refs:CMP_CR1_PMODE_MASK (Results 1 – 25 of 26) sorted by relevance

12

/hal_nxp-2.7.6/mcux/drivers/kinetis/
Dfsl_cmp.c84 …tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_… in CMP_Init()
87 tmp8 |= CMP_CR1_PMODE_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/drivers/imx/
Dfsl_cmp.c84 …tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_… in CMP_Init()
87 tmp8 |= CMP_CR1_PMODE_MASK; in CMP_Init()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
DMKL25Z4.h641 #define CMP_CR1_PMODE_MASK (0x10U) macro
643 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
DMK22F51212.h938 #define CMP_CR1_PMODE_MASK (0x10U) macro
944 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
DMKW24D5.h1192 #define CMP_CR1_PMODE_MASK (0x10U) macro
1194 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
DMKW22D5.h1192 #define CMP_CR1_PMODE_MASK (0x10U) macro
1194 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
DMKW31Z4.h1007 #define CMP_CR1_PMODE_MASK (0x10U) macro
1009 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
DMK64F12.h6609 #define CMP_CR1_PMODE_MASK (0x10U) macro
6615 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
DMKW40Z4.h776 #define CMP_CR1_PMODE_MASK 0x10u macro
779 …DE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
DMKW40Z4_extension.h2236 #define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
2240 #define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
DMKW21Z4.h936 #define CMP_CR1_PMODE_MASK (0x10U) macro
938 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
DMKW41Z4.h1007 #define CMP_CR1_PMODE_MASK (0x10U) macro
1009 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
DMKW20Z4.h776 #define CMP_CR1_PMODE_MASK 0x10u macro
779 …DE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
DMKW30Z4.h776 #define CMP_CR1_PMODE_MASK 0x10u macro
779 …DE(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR1_PMODE_SHIFT))&CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
DMKV56F24.h5998 #define CMP_CR1_PMODE_MASK (0x10U) macro
6004 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
DMK80F25615.h4856 #define CMP_CR1_PMODE_MASK (0x10U) macro
4862 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
DMKV58F24.h6002 #define CMP_CR1_PMODE_MASK (0x10U) macro
6008 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
DMK82F25615.h4850 #define CMP_CR1_PMODE_MASK (0x10U) macro
4856 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
DMK66F18.h5651 #define CMP_CR1_PMODE_MASK (0x10U) macro
5657 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1021/
DMIMXRT1021.h8795 #define CMP_CR1_PMODE_MASK (0x10U) macro
8801 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1024/
DMIMXRT1024.h8777 #define CMP_CR1_PMODE_MASK (0x10U) macro
8783 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1051/
DMIMXRT1051.h8614 #define CMP_CR1_PMODE_MASK (0x10U) macro
8620 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1052/
DMIMXRT1052.h9833 #define CMP_CR1_PMODE_MASK (0x10U) macro
9839 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1061/
DMIMXRT1061.h9803 #define CMP_CR1_PMODE_MASK (0x10U) macro
9809 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
/hal_nxp-2.7.6/mcux/devices/MIMXRT1062/
DMIMXRT1062.h11171 #define CMP_CR1_PMODE_MASK (0x10U) macro
11177 …) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)

12